Advanced Low Pin Count Test Architecture for Efficient Multi-Site Testing

Abstract

With the rapidly increasing test time of semiconductor testing, the trend is currently toward improving test parallelism by exploiting multi-site testing. However, excessive test I/O channels and test power consumption lead to the degradation of multi-site testing efficiency owing to the limited number of tester I/Os and power capacity. In this paper, we present an advanced low pin count test architecture for efficient multi-site testing in semiconductors. To achieve this, the scan chain routing method is first exploited to reduce the power consumption during scan-based testing through a cluster-based approach, which is compatible with the test compression architecture. Subsequently, a new test compression architecture is proposed to encode test patterns and enable the testing of each device-under-test (DUT) through a low input test pin count by using the unique properties of the proposed tri-state detector and boundary scan architecture. The experimental results show the decrease in the test I/O requirements and test power consumption. Based on these improvements, the test application time (TAT) was significantly reduced for ISCAS'89 and IWLS'05 OpenCores benchmark circuits compared to the previous methods, without a heavy burden on the additional H/W area and routing overhead.