Low Parasitic Inductance Research Articles

Multichip Parallel Double-Sided Cooling Silicon Carbide Power Module With Low Parasitic Inductance and Balanced Dynamic Current

Multichip Parallel Double-Sided Cooling Silicon Carbide Power Module With Low Parasitic Inductance and Balanced Dynamic Current

Thermal cycling characterization of an integrated low-inductance GaN eHEMT power module

To exploit the potential of wide-bandgap semiconductors in high-frequency applications, innovative packaging designs are developed to minimize the parasitic inductance of power modules. This study presents an integrated power module with a hybrid PCB/DBC structure, which uses top-side cooling prepackaged GaN enhancement-mode high-electron-mobility transistors. The module achieves a remarkably low parasitic inductance of 2.65 nH. However, there is relatively scarce research on the reliability of this heterostructure, particularly its sensitivity to thermomechanical stress due to the coefficients of thermal expansion mismatch among material interfaces. In this work, the thermal cycling characteristics of the integrated power module are comprehensively investigated. Electrical and thermal parameters were periodically and separately measured offline on a simplified package to monitor the health conditions and decouple possible synergy and competition effects among the failure modes from all packaging components. A thorough failure analysis was conducted using nondestructive visual inspections and scanning acoustic microscopy, complemented by destructive cross-sectional examination and scanning electron microscopy. The findings identified the delamination of the DBC upper copper layer, which exhibited a conchoidal fracture interface, as the primary factor that contributed to the failure of the power module with increased thermal resistance. Furthermore, the study dissected its initiation and propagation mechanisms. This investigation provides valuable insights for the development of more reliable low-inductance power module designs.

Design of Half-Bridge Switching Power Module Based on Parallel-Connected SiC MOSFETs for LLC Resonant Converter with Symmetrical Structure and Low Parasitic Inductance

SiC MOSFETs are used in many power conversion applications because of their superior characteristics, such as fast switching speed, low on-resistance, and high operating temperature. In certain high-power systems, SiC MOSFETs are connected in parallel to enhance their current capacity and power efficiency. However, compared with Si-based devices, the current imbalance caused by the parasitic inductance difference becomes more severe when driving SiC MOSFETs in parallel, owing to the fast switching speed. Furthermore, the power loop inductance imbalance that occurs when constructing a half-bridge with parallel SiC MOSFETs has rarely been addressed in previous studies. In this study, a half-bridge switching power module based on parallel-connected SiC MOSFETs is proposed to solve the current imbalance through a symmetric structure of the gate and power loops. The effects of the magnitude and imbalance of the gate and power loop inductances in the half-bridge structure based on parallel-connected devices are also explained. A detailed printed circuit board layout of the proposed switching power module is provided, and the inductance symmetry is verified through simulations. A double-pulse test is conducted to verify the current-balancing capability of the proposed switching power module. In addition, an LLC resonant converter is designed using the proposed switching power module, and the power loss between parallel SiC MOSFETs is compared. The experimental results indicate the total power loss error between the parallel-connected SiC MOSFETs of the proposed power module is only 1.94%.

A 2.5D Multichip SiC MOSFET Power Module With Low Parasitic Inductance and High Dynamic Current Sharing Performance

A 2.5D Multichip SiC MOSFET Power Module With Low Parasitic Inductance and High Dynamic Current Sharing Performance

Energy Extraction System for the Superconductive Solenoid with Current 5100 A and Stored Energy 22 MJ

At the FAIR (Facility for Antiproton and Ion Research, Darmstadt, Germany) accelerator complex under construction, one of the key experiments is the PANDA experiment. The main field of the PANDA spectrometer is provided by a superconducting solenoid. The energy of the magnetic field stored in a superconducting solenoid reaches 22 MJ at an operating current of 5100 A. In the case of the transition of the superconducting cable used for the solenoid winding into a resistive state, the safe extraction of stored energy is required to protect the magnet. The energy extraction system proposed by the authors provides energy dissipation inside the external dump resistor, and not in the section of the superconducting cable that has passed into resistive state, while preventing its damage. The most critical elements of the energy extraction system are the current breaker, with the help of which the dump resistor is introduced into the power circuit of the superconducting solenoid, and the dump resistor itself. A modernized three-phase circuit breaker was chosen as current breaker. A unique design of the energy extraction system including dump resistor with a low parasitic inductance has been developed.

On-Site Estimation of Thermal Resistance Degradation of Double-Sided Cooling (DSC) Power Modules Under Power Cycling Conditions

Double-sided cooling (DSC) power modules are increasingly used due to their superior cooling capability and low parasitic inductance. However, the DSC modules have multiple interconnections for heat dissipation, so it is challenging to accurately monitor the thermal resistance degradation of each interconnection under power cycling conditions. An estimation method considering the self-heating and thermal coupling effects of DSC power modules is proposed based on a traditional lumped RC thermal impedance network. The proposed method combining a recursive least squares algorithm with a thermal network model can well evaluate the thermal resistance of each interconnection and their variations on-site during power cycling tests. The lifetime of DSC power modules for power cycling tests could be overestimated if using the 20% increment in overall thermal resistance of DSC modules as a failure criterion.

A High Power Density Double-Side-End Double-Sided Bonding SiC Half-Bridge Power Module

Silicon Carbide (SiC) power module with lower loop inductance, better dynamic current sharing properties and better thermal performance will contribute to achieve high power density three phase inverter in medium voltage applications. Inspired by the concept of double-side-end busbar, a novel double-side-end double sided bonding power module is proposed in this paper. For three chips parallel situation, double-side-end structure decreases parasitic inductance by 40% compared to that of traditional baseline structure. Besides lower parasitic inductance, novel structure also has better dynamic current sharing properties. To explain these dynamic current sharing phenomena, an equivalent source inductance model considering mutual inductance is proposed in this paper. A 1200V 10mΩ SiC double-side-end double sided bonding half-bridge power module is designed, fabricated and tested. Proposed power module realizes 3nH power loop inductance. Furthermore, to realize practical application of the novel power module, a novel compact two-level three-phase integration architecture based on novel power module is also proposed. With the help of the double-sided direct-cooling method and double-side-end busbar, proposed architecture will help to realize better performance.

FEA-Dominant Reliability and Lifetime Model of Double-Sided Cooling SiC Power Module

Owing to the low parasitic inductance, high power density, and excellent heat extraction performance, double-sided cooling (DSC) is regarded as a promising packaging solution for the silicon carbide (SiC) power module. Nevertheless, given the unclear failure mechanism and missed lifetime model, the reliability assessment and lifetime prediction of the DSC SiC power module remains a concern. Besides, the accelerated aging test generally used for the reliability assessment of the SiC power module is extremely time-consuming and costly. Therefore, the obstacles mentioned before limit the development and deployment of the DSC SiC power module. Aiming to fulfill these research gaps, based on the aging mechanism and failure criterion of packaging materials, the lifetime model of the DSC SiC power module is proposed in this paper. Comparative experiments show that the relative error of the FEA-dominated model is less than 6%. Moreover, the stress property and creep principle of the solder layer in SiC and Si power modules are assessed, respectively. Besides, the lifetime models of SiC and Si power modules applying different packaging materials are created. It is found that the lifetime of the DSC power module is twice that of the single-sided cooling (SSC) counterpart. Furthermore, applying the same packaging, the lifetime of the SiC power module decreases by 70% compared with the Si counterpart. In addition, the lifetime of the DSC SiC power module affected by different materials such as ceramic and spacer is studied in order to enhance its reliability.

Ultra-thin on-chip ALD LiPON capacitors for high frequency application

Multi-layer ceramic capacitors have been used for high frequency decoupling application due to a lower overall impedance leading to fast current response. However, high parasitic inductance limits the application of these capacitors in ultra-high frequency domain. Thus, Multlayer Ceramic Capacitors (MLCCs) are placed close to the IC to improve circuit efficiency and reduce inductance. With next generation applications, the demand for frequency range has further increased which not only requires enhanced capacitor material but improved manufacturing techniques to limit the inductive path. Here, we demonstrate ALD of two different polymorphs of ultra-thin film lithium phosphorus oxynitride (LiPON) as an inorganic solid state electrolyte (SSE) for on chip capacitors for decoupling application. Both the LiPON capacitors shows an electric double layer behavior with a capacitance of 15 μF/cm2 and a low leakage current (<20 nA/cm2) at 2V. The LiPON shows EDLC behavior up to 10 kHz and beyond, both the polymorphs show an electrostatic behavior with a high dielectric constant (14). This dual frequency behavior along with low parasitic inductance and on chip integration allows for operation in extended frequency ranges.

Design and Implementation of Low Parasitic Inductance Bias Circuit for High-Power Pulsed Power Amplifiers

This article presents a wideband bias circuit with low parasitic inductance for high-power pulsed amplifiers. The proposed bias circuit works similarly to the traditional bias circuit in that it can ensure the transmission of microwaves from the power amplifier to the load while preventing the transmission of microwaves from the power amplifier to the power supply. By making the bias line shorter and the transmission line wider than the traditional bias circuit, the proposed bias circuit reduces its parasitic inductance. The reduction of parasitic parameters is critical for reducing the drain voltage overshoot of the high-power pulse power amplifier and ensuring its safety. The simulation results demonstrate that the proposed bias circuit has a lower parasitic inductance and a wider bandwidth. To validate the theory and simulation results, the traditional and the proposed bias circuits are fabricated using microstrip circuits. Both the simulation and experimental results indicate that the proposed bias circuit has a one-third lower parasitic inductance than the traditional bias circuit. Furthermore, the proposed bias circuit has a wider bandwidth.

Design and Evaluation of a Face-Down Embedded SiC Power Module With Low Parasitic Inductance and Low Thermal Resistance

This letter proposed an embedded silicon carbide (SiC) power module with low parasitic inductance and low thermal resistance for high-frequency and high-temperature applications. The SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s were oriented in a face-down configuration with Cu connecting blocks, contributing to better switching performance and heat dissipation. The simulation results showed that the total parasitic inductance was lower than 300 pH. Double pulse test and thermal resistance experiments compared with a commercial package showed that the switching loss and the junction-to-case resistance of the proposed module were reduced by 23% and 35%, respectively.

Low Parasitic-Inductance Packaging of a 650 V/150 A Half-Bridge Module Using Enhancement-Mode Gallium-Nitride High Electron Mobility Transistors

Because of their fast-switching speed and small die size, gallium-nitride high electron mobility transistors are challenging to package for low parasitic inductance and high heat dissipation in power electronics applications. In this article, a packaging technique was developed for making half-bridge modules of a 650 V, 150 A enhancement-mode gallium-nitride power transistor. The package consists of the device chips interconnected between a printed circuit board and an aluminum-nitride direct-bonded copper substrate. The dice are bonded on the insulated ceramic substrate by silver-sintering to ensure high thermal performance and joint reliability. The source, drain, and gate pads are connected by silver-sintering gold-plated pins or silver rods, which are aligned by holes or grooves in the circuit board. For electrical insulation and mechanical robustness, the space surrounding the device is filled by injecting and curing an underfill polymer. Electrical and thermal simulations of the package show that the half-bridge module has a 1.122 nH power-loop inductance, and 0.099 °C/W junction-to-case thermal resistance. Packages of the half-bridge module were fabricated, and their static and dynamic performances were characterized.

Printed circuit board embedded power semiconductors: A technology review

Embedding power semiconductor devices into printed circuit boards (PCB) provides several benefits compared to conventional packaging technologies. Integrating the semiconductor dies into the circuit board reduces the converter size. This results in short current loops, enabling low interconnection resistances and parasitic inductances. Both contribute to a higher system-level efficiency, as conduction and switching losses are reduced. Moreover, the use of thick Cu substrates allows efficient heat removal, due to a low thermal resistance. Therefore, PCB embedding has received a lot of attention in the power electronics community for more than a decade. This article aims to provide a comprehensive review of the scientific literature on the topic ranging from basic fabrication technology over module or system-level demonstrators for electrical and thermal testing to reliability studies. Performance indicators, such as the commutation loop inductance Lσ, the chip area independent thermal resistance Rth × Achip, allow a comparison of different approaches and benchmarking with conventional power modules. Several publications report stray inductances below 1 nH and chip area independent thermal resistances in the range of 20…30 mm²K/W.

Review of the designs in low inductance SiC half‐bridge packaging

Silicon carbide (SiC) device has become the primary choice for high-efficiency power electronic equipment due to its excellent performance. However, its higher switching frequency and faster switching speed have also incurred new challenges, such as low parasitic inductance packaging. Despite a significant amount of literature to overview the low parasitic inductance packages, most of them focus on total parasitic inductance from different packaging technology. Here, from the viewpoint of partial inductance which includes gate loop, power loop and common source, the designs for different inductances are surveyed. The power loop is further discussed from power terminals, bonding wires and direct bonded copper (DBC) conductor traces. The effects and sources of these inductances are analyzed. Furthermore, the typical design solutions to reduce the inductances are summarized. Finally, the challenges of SiC packages are presented.

Switching and Heat-dissipation Performance Analysis of an LTCC-based Leadless Surface Mount Package

A leadless surface mount package was developed to enhance the switching and heat-dissipation properties of a power semiconductor. The package was implemented through a low-temperature co-fired ceramic (LTCC)-based multilayer circuit substrate that could form embedded cavities. A silicon carbide (SiC) Schottky barrier diode (SBD) bare die was attached to the cavity in the LTCC substrate. Chip interconnection was realized using a wide and thick copper (Cu) clip with a low parasitic inductance and electrical resistance compared to those of a conventional wire. Silver-filled multiple vias and wide metal planes were used to reduce the electrical parasitic effects and enhance the heat-dissipation of the package. The DC and dynamic characteristics of the 600 V/10 A-class SiC SBD package involving the proposed technologies were evaluated. The dynamic test results indicated that the reverse recovery charge (Qrr) was 18.7% lower than that of a traditional TO-220 packaged product with the same bare die. Furthermore, two leadless commercial products and he proposed package prototype were applied to a power factor correction (PFC) converter, and the power loss and heat-dissipation performances were compared. The proposed package exhibited a lower loss and higher heat dissipation than those of the commercial products.

Design of Low Inductance SiC-MOS/Si-IGBT Hybrid Module for PV Inverters

In this paper, design of a low parasitic inductance T-type SiC-MOS/Si-IGBT hybrid module for PV inverters is studied. Current commutation loops and self- and mutual inductances model of the hybrid module are analyzed. Then stacked substrates structures with vertical power commutation loop to reduce parasitic inductance are identified and compared. Finally, a hybrid module with stacked bond wire substrates structure is built and test results are provided to verify the design.

A novel double-sided cooling packaging structure of SiC-based half bridge module integrating the laminated busbar

This paper presents a novel double-sided cooling SiC-based half-bridge (HB) module with laminated busbar. The novelty of this module lies in the integration of a laminated busbar which can result in a significant reduction of the module parasitic inductance. Moreover, a 3D vertical structure design can reduce the commutation loop area inside the module, thereby further achieving a lower commutation loop inductance. Meanwhile, this module achieves wire-free bonding that can improve the reliability of the power module to a certain extent. A fan-shaped DBC layout is designed to ensure the symmetrical layout of the paralleled chips, which can realize a better current sharing performance. In fact, an unbalanced junction temperature can also affect the current balance of each parallel device, resulting in unequal turn-on and turn-off losses. Therefore, a three-outlet circular water-cooled heat sink is proposed to ensure the junction temperature balance of the parallel chips, which is demonstrated by thermal simulation. Then, by the Ansys Q3D, the extracted parasitic inductance of the module is about 5.63 nH, and the imbalance degree between each parallel branch is about 5.8%. Finally, the low parasitic inductance and highly symmetry of the module are verified by the experimental tests.

A SiC Double-Sided Stacked Wire-Bondless Power Module for High-Frequency Power Electronic Applications

Abstract This article reports a double-sided stacked wire-bondless power module package for silicon carbide (SiC) power devices to achieve low parasitic inductance and improved thermal performance for high-frequency applications. The design, simulation, fabrication, and characterization of the power module are presented. A half-bridge module based on the SiC power MOSFETs is demonstrated with minimized parasitic inductance. Double-sided cooling paths are used to maximize heat dissipation. Besides conventional packaging materials used in the power module fabrication, a low-temperature cofired ceramic (LTCC) and nickel-plated copper balls are used in this module package. The LTCC acts as an interposer providing both electrical and thermal routings. The nickel-plated copper balls replace bond wires as the electrical interconnections for the SiC power devices. The electrical and thermo-mechanical simulations of the power module are performed, and its switching performance is evaluated experimentally.

High-Temperature Characterizations of a Half-Bridge Wire-Bondless SiC MOSFET Module

SiC MOSFET allows higher temperature capability with higher switching efficiency than that of conventional Si devices, due to its superior electrical and thermal properties. Nevertheless, there are few reports on the systematic characterization of the SiC MOSFET power module operating at high-temperature. In this paper, a SiC MOSFET power module with planar interconnection was designed and fabricated to achieve low parasitic inductance and improved thermal performance. The static and dynamic performance of the SiC power module were characterized at 200°C. The thermal resistance of the double-sided cooling power module is 28.5% lower than that of the one with single-sided cooling.

Vertically Stacked, Flip-Chip Wide Bandgap MOSFET Co-Optimized for Reliability and Switching Performance

Silicon carbide (SiC) wide-bandgap semiconductors (WBGs) offer a significant improvement in high voltage and high-temperature stability; however, their associated packaging often can impede electrical performance and reliability. In this study, a new flip-chip package, implementing a vertically oriented metal oxide semiconductor field effect transistor (MOSFET) was investigated to achieve co-optimized thermomechanical reliability with low parasitic inductance. The architecture improves upon wire-bonded packages by allowing for top-side cooling and reduced power loop inductance. Herein, the design effects of solder material and diameter as well as pitch size and drain connector geometry on thermal cycling reliability of the device were investigated using finite-element methods. Additionally, thermal resistance in association with a parasitic inductance of varying drain connector architectures is compared while utilizing symmetry to facilitate manufacturability. By considering the complex effects of geometry and material, the optimal architecture was selected and fabricated. When comparing to a prior flip-chip design effort, this simulation-based design optimization was able to improve the solder fatigue life up to 11 times while reducing parasitic inductance by 30 times. Experimentally, the associated electrical performance of the novel device showed improved switching behavior in double-pulse testing of a half-bridge module, with nearly negligible overshoot voltage on switching, where an equivalent discrete package exhibited ~100% overshoot and ~24% inductance improvement at the module level.