Thermal cycling characterization of an integrated low-inductance GaN eHEMT power module

Abstract

To exploit the potential of wide-bandgap semiconductors in high-frequency applications, innovative packaging designs are developed to minimize the parasitic inductance of power modules. This study presents an integrated power module with a hybrid PCB/DBC structure, which uses top-side cooling prepackaged GaN enhancement-mode high-electron-mobility transistors. The module achieves a remarkably low parasitic inductance of 2.65 nH. However, there is relatively scarce research on the reliability of this heterostructure, particularly its sensitivity to thermomechanical stress due to the coefficients of thermal expansion mismatch among material interfaces. In this work, the thermal cycling characteristics of the integrated power module are comprehensively investigated. Electrical and thermal parameters were periodically and separately measured offline on a simplified package to monitor the health conditions and decouple possible synergy and competition effects among the failure modes from all packaging components. A thorough failure analysis was conducted using nondestructive visual inspections and scanning acoustic microscopy, complemented by destructive cross-sectional examination and scanning electron microscopy. The findings identified the delamination of the DBC upper copper layer, which exhibited a conchoidal fracture interface, as the primary factor that contributed to the failure of the power module with increased thermal resistance. Furthermore, the study dissected its initiation and propagation mechanisms. This investigation provides valuable insights for the development of more reliable low-inductance power module designs.