Low-noise Instrumentation Amplifier Research Articles

A novel tunable capacitively-copuled instrumentation amplifier with 14.4 nV/ [formula omitted] z) noise and 190.47 nW micro-power for ECG applications

This paper describes a low-power, low-noise capacitively-coupled instrumentation amplifier (CCIA) designed for capturing biopotential signals. The main advantage of proposed design are as (i) CCIA based on new IA has been proposed, (ii) the lower cutoff frequency has been improved by adding MOS based resistor, (iii) gm enhancement circuit is added in operational transconductance amplifier (OTA) based fully differential difference amplifier (FDDA)to improve gain and bandwidth. The DC electrode-offset voltage is reduced and the input impedance is increased by using feedback mechanism. Cadence EDA tool is used to analyze the findings of the proposed CCIA's in 0.18 μm, CMOS technology with a 1.8 V power supply. The proposed CCIA architecture has an adjustable mid-band gain from 52.55 to 61.11 dB for bias voltage ranges from 0.1 to 0.6 V, frequency range of 0.06 Hz–1.72 kHz, and a CMRR of 122 dB. The proposed CCIA has a total power dissipation of 190.47 nW and equivalent input referred noise (IRN) of 14.4 nV/sqrtHz at 0.01 Hz. It only occupies 0.01 mm2 of core area. To assess the robustness of suggested design, PVT analysis, post layout simulation and a comparison with previously published works demonstrates the competence of the design.

A 0.26 [formula omitted]Vrms instrumentation amplifier based on discrete-time DC servo loop with successive-approximation-compensation technique and Chopper DAC Array

A low-noise instrumentation amplifier for bio-signal recording is proposed in this paper. One of the significant disturbances, electrode DC offset, is suppressed using the proposed successive-approximation-compensation (SAC) circuit based on a discrete-time DC servo loop with Chopper DAC Array. Firstly, the DC offset at the output is quantified using the SAR quantizer. Next, the digital code produced by the SAR quantizer is used to control the chopper DAC array. Finally, a suitable compensation voltage is generated and used directly to correct the electrode DC offset at the input of the chopper amplifier. By using the proposed compensation technique, the first-stage chopper amplifier’s quiescent operating state is unaffected. When a 50-mV DC offset voltage exists at the differential input, the SAC circuit can compensate the DC offset voltage close to zero in a relatively short time. At the same time, there are fewer capacitors, which significantly decrease the area consumption. The proposed instrumentation amplifier is implemented in a standard 0.18μm CMOS process. The experiment results show that over a bandwidth from 0.1 Hz to 100 Hz, an input referred noise of 0.26 μVrms at the TT corner has been attained. The total power consumption is about 13.72 μW at the supply voltage of 1.8 V. The gain of the instrumentation amplifier is about 39.15 dB and its Noise Efficiency Factor (NEF) is 2.76.

Novel tunable current feedback instrumentation amplifier based on BBFC OP-AMP for biomedical applications with low power and high CMRR

The paper presents a novel low power, low noise and high CMRR current feedback instrumentation amplifier (CFIA) design for biomedical signal acquisition i.e. EEG/ECG applications is presented. The proposed instrumentation amplifier performance is evaluated using 0.18μm, CMOS technology with 1.8 V supply and results are obtained in Cadence EDA tool. The proposed CFIA is implemented using a dual output bandwidth boosted folded cascode operational amplifier (BBFC OP-AMP) active block. In this paper the proposed CFIA performance parameters has been considered for optimization to get better results by using the idea of signal to noise ratio (SNR) with Taguchi design of experiments (Taguchi DoE) and analysis of variance (ANOVA) to estimate the most important independent variable which control the performance of the design. The bias voltage, channel length and width of input MOS transistors have been selected to optimize the proposed circuit performance. The proposed CFIA structure have 50.33 to 69.67 dB tunable differential gain, common mode rejection ratio (CMRR) of 143.19 dB, tunable bandwidth of 148.24 kHz to 1.31 MHz, dynamic range (DR) of 74.31 dB and 297.73 dB of figure of merit (FoM). The CFIA shows an equivalent input referred noise (IRN) of 0.586 μV at 0.1 Hz to 148.24 kHz frequency range, with total power dissipation of 102.73 μW and occupies 8194μm2 of core area. The simulation results of the proposed CFIA are close to the predicted solution obtained from ANOVA. The PVT analysis and post layout simulation has been performed to check the robustness of the proposed design. The proposed design has been compared with the other existing literature which shows the competence of the design.

ECG Arrhythmia Classification on an Ultra-Low-Power Microcontroller.

Wearable biomedical systems allow doctors to continuously monitor their patients over longer periods, which is especially useful to detect rarely occurring events such as cardiac arrhythmias. Recent monitoring systems often embed signal processing capabilities to directly identify events and reduce the amount of data. This work is the first to document a complete beat-to-beat arrhythmia classification system implemented on a custom ultra-low-power microcontroller. It includes a single-channel analog front-end (AFE) circuit for electrocardiogram (ECG) signal acquisition, and a digital back-end (DBE) processor to execute the support vector machine (SVM) classification software with a Cortex-M4 CPU. The low-noise instrumentation amplifier in the AFE consumes 1.4 μW and has an input-referred noise of 0.9 μV RMS. The all-digital time-based ADC achieves 10-bit effective resolution over a 250-Hz bandwidth with an area of only 900 μm 2. The classification software reaches a sensitivity of 82.6% and 88.9% for supraventricular and ventricular arrhythmias respectively on the MIT-BIH arrhythmia database. The proposed system has been prototyped on the SleepRider SoC, a 28-nm fully-depleted silicon on insulator (FD-SOI) 3.1-mm 2 chip. It consumes 13.1 μW on average from a 1.8-V supply.

A Low-Noise Instrumentation Amplifier With Built-in Anti-Aliasing for Hall Sensors

We present a compact, versatile Hall readout system with digital output, fully integrated in 180nm technology. The core of the system is an instrumentation amplifier architecture that provides inherent anti-aliasing filtering, where the anti-aliasing characteristic is locked into a shape that maximally prevents aliasing to low frequencies. The efficiency for blocking out-of-band white noise is comparable to that of a second-order filter, eliminating the need for an explicit anti-aliasing filter before the ADC. Chopping/spinning is applied for up-modulating offset and 1/f noise to just beyond the signal band. A mostly-digital ripple reduction loop (RRL) is added for mitigating offset-related dynamic range limitations. In this, a bilinear integrator is introduced for eliminating the impact of the RRL on the system's DC gain. Moreover, the resolution of the DAC generating the analog offset compensation is reduced significantly, and the effect thereof is eliminated by digital noise cancellation logic. The one-step amplification and the simple, low-resolution DAC for offset compensation both aid in keeping the area footprint low: the analog circuits (including DAC and ADC) only occupy 0.21mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Notable performance characteristics are an input-referred noise floor of 55nT/ √{Hz} within a 410kHz bandwidth, a current consumption of only 5.1mA, and a 47dB dynamic range. The amplifier architecture can be easily applied as an analog preconditioning circuit in other sensor readout situations as well.

A 197.1-μW Wireless Sensor SoC With an Energy-Efficient Analog Front-End and a Harmonic Injection-Locked OOK TX

This paper presents an integrated ultra-low-power (ULP) wireless sensor system-on-chip (SoC) that can be used for voltage sensing in both Internet of Things applications and bio-potential monitoring. In order to increase the energy efficiency of the analog front-end (AFE), we propose a noise and power efficient push-pull low noise instrumentation amplifier (LNIA) with a built-in ripple reduction loop based on capacitor reuse. A low-power ISM-band harmonic injection locked on-off-keying transmitter (OOK-TX) is also implemented for energy efficient wireless connectivity. Circuit implementations, design considerations, and detailed analysis are presented to improve the overall energy efficiencies of the SoC including the AFE, TX and, the power management unit. The proposed ULP-SoC is fabricated in 130 nm CMOS technology with a total area of 1.92 mm2. The total power consumption of the proposed system-on-chip is $197.1~\mu \text{W}$ which is one of the lowest among state-of-the-art wireless sensor SoC.

A Chopper Stabilization Audio Instrumentation Amplifier for IoT Applications

A low-noise instrumentation amplifier dedicated to a nano- and micro-electro-mechanical system (M&amp;NEMS) microphone for the use in Internet of Things (IoT) applications is presented. The piezoresistive sensor and the electronic interface are respectively, silicon nanowires and an instrumentation amplifier. To design an instrumentation amplifier for IoT applications, different trade-offs are discussed like power consumption, gain, noise and sensitivity. Because the most critical noisy block is the amplifier, a delay-time chopper stabilization (CHS) technique is implemented around it to eliminate its offset and 1/f noise. The low-noise instrumentation amplifier is implemented in a 65-nm CMOS (Complementary metal–oxide–semiconductor) technology. The supply voltage is 2.5 V while the power consumption is 0.4 mW and the core area is 1 mm2. The circuit of the M&amp;NEMS microphone and the amplifier was fabricated and measured. From measurement results over a signal bandwidth of 20 kHz, it achieves a signal-to-noise ratio (SNR) of 77 dB.

A 0.6-µW Chopper Amplifier Using a Noise-Efficient DC Servo Loop and Squeezed-Inverter Stage for Power-Efficient Biopotential Sensing.

To realize an ultra-low-power and low-noise instrumentation amplifier (IA) for neural and biopotential signal sensing, we investigate two design techniques. The first technique uses a noise-efficient DC servo loop (DSL), which has been shown to be a high noise contributor. The proposed approach offers several advantages: (i) both the electrode offset and the input offset are rejected, (ii) a large capacitor is not needed in the DSL, (iii) by removing the charge dividing effect, the input-referred noise (IRN) is reduced, (iv) the noise from the DSL is further reduced by the gain of the first stage and by the transconductance ratio, and (v) the proposed DSL allows interfacing with a squeezed-inverter (SQI) stage. The proposed technique reduces the noise from the DSL to 12.5% of the overall noise. The second technique is to optimize noise performance using an SQI stage. Because the SQI stage is biased at a saturation limit of 2VDSAT, the bias current can be increased to reduce noise while maintaining low power consumption. The challenge of handling the mismatch in the SQI stage is addressed using a shared common-mode feedback (CMFB) loop, which achieves a common-mode rejection ratio (CMRR) of 105 dB. Using the proposed technique, a capacitively-coupled chopper instrumentation amplifier (CCIA) was fabricated using a 0.18-µm CMOS process. The measured result of the CCIA shows a relatively low noise density of 88 nV/rtHz and an integrated noise of 1.5 µVrms. These results correspond to a favorable noise efficiency factor (NEF) of 5.9 and a power efficiency factor (PEF) of 11.4.

432 nW per Channel 130 nV/rtHz ECG Acquisition Front End With Multifrequency Chopping

An ultralow-power low-noise analog front end (AFE) for ECG signal acquisition is demonstrated. The key to its performance is a multifrequency chopping technique that helps to significantly reduce power consumption by frequency-division multiplexing of two channels in a single low-noise instrumentation amplifier (IA). A complete two-channel AFE, chopped at frequencies of 4 and 8 kHz, is implemented in a 0.13- $\mu \text{m}$ CMOS technology from United Microelectronics Corporation. A current-reuse technique is employed in the first stage of the IA to achieve area savings and improve interchannel isolation. Experimental results show that the front end achieves an input-referred noise voltage density of 130 nV/rtHz while consuming current of 360 nA per channel from a 1.2-V power supply. The 1/f noise corner of the system is around 10 Hz, and the measured common-mode rejection ratio (CMRR) is 98 dB.

Fully Integrated Bidirectional CMOS-MEMS Flow Sensor With Low Power Pulse Operation

Leveraging More-than-Moore technology, we demonstrate an integrated CMOS MEMS flow sensor via a very compact system on chip (SoC) that can sense the bidirectional N2 gas flow. Our SoC features a very low-noise instrumentation amplifier that is implemented on a CMOS wafer and serves as a readout integrated circuit for a thermoresistive micro-calorimetric flow sensor which is fabricated on a MEMS wafer. A compact heterogeneous integration is achieved by combining the two wafers via the proprietary InvenSense AlN process. The measured sensitivity of our CMOS MEMS flow sensor is 98 mV/sccm which is three times better than the state-of-the-art counterpart. The flow range measured by our SoC is from −26 to 26 m/s (from −50 to 50 sccm). Moreover, the pulsed heater operation makes this proposed SoC flow sensor a very low power (<9 mW) and, thus, a promising candidate for the Internet-of-Things applications in smart home/green buildings.

A Flexible 12-Lead/Holter Device with Compression Capabilities for Low-Bandwidth Mobile-ECG Telemedicine Applications.

In recent years, a number of proposals for electrocardiogram (ECG) monitoring based on mobile systems have been delivered. We propose here an STM32F-microcontroller-based ECG mobile system providing both long-term (several weeks) Holter monitoring and 12-lead ECG recording, according to the clinical standard requirements for these kinds of recordings, which in addition can yield further digital compression at stages close to the acquisition. The system can be especially useful in rural areas of developing countries, where the lack of specialized medical personnel justifies the introduction of telecardiology services, and the limitations of coverage and bandwidth of cellular networks require the use of efficient signal compression systems. The prototype was implemented using a small architecture, with a 16-bits-per-sample resolution. We also used a low-noise instrumentation amplifier TI ADS1198, which has a multiplexer and an analog-to-digital converter (16 bits and 8 channels) connected to the STM32F processor, the architecture of which incorporates a digital signal processing unit and a floating-point unit. On the one hand, the system portability allows the user to take the prototype in her/his pocket and to perform an ECG examination, either in 12-lead controlled conditions or in Holter monitoring, according to the required clinical scenario. An app in the smartphone is responsible for giving the users a friendly interface to set up the system. On the other hand, electronic health recording of the patients are registered in a web application, which in turn allows them to connect to the Internet from their cellphones, and the ECG signals are then sent though a web server for subsequent and ubiquitous analysis by doctors at any convenient terminal device. In order to determine the quality of the received signals, system testing was performed in the three following scenarios: (1) The prototype was connected to the patient and the signals were subsequently stored; (2) the prototype was connected to the patient and the data were subsequently transferred to the cellphone; (3) the prototype was connected to the patient, and the data were transferred to the cellphone and to the web via the Internet. An additional benchmarking test with expert clinicians showed the clinical quality provided by the system. The proposed ECG system is the first step and paves the way toward mobile cardiac monitors in terms of compatibility with the electrocardiographic practice, including the long-term monitoring, the usability with 12 leads, and the possibility of incorporating signal compression at the early stages of the ECG acquisition.

An Energy-Efficient and Reconfigurable Sensor IC for Bio-Impedance Spectroscopy and ECG Recording

This paper presents a low power reconfigurable IC for wearable health devices that perform bio-impedance (BioZ) spectroscopy, respiration, and ECG signals measurement. The IC consists of a broadband excitation current source (I-DAC) and a power efficient readout circuit (RO). Both are highly scalable to mitigate the tradeoff among noise, dynamic range, speed, power, and safe current limits. On circuit level, the I-DAC supports two broadband excitation modes based on maximum length sequence (MLS), a flexible selection of frequency points, bandwidth, and current magnitude. The RO employs a low noise instrumentation amplifier and a reconfigurable 8-to-12 bit ADC for flexible sensitivity, dynamic range and speed with an automatic scaling of the power consumption. On system level, calibration of the entire circuit chain, oversampling and MLS averaging further improve the bandwidth, accuracy and sensitivity of BioZ spectroscopy beyond the intrinsic circuit performance. As a result, the BioZ sensor IC achieves 2 $\text{m}\Omega $ sensitivity within 3.3 $\text{m}\Omega $ – $100~\Omega $ range and $0.6~\Omega $ sensitivity within $3.3~\Omega $ –100 $\text{k}\Omega $ range. The BioZ spectroscopy spans up to 125 kHz while consuming $155~\mu \text{W}$ . Furthermore, this IC can measure respiration and ECG simultaneously at a lower sampling rate of 20 kS/s while consuming $31~\mu \text{W}$ . Compared to prior art, to the best of our knowledge, this IC is the only work that can measure BioZ and ECG simultaneously with a single readout channel while consuming the lowest power and offering the highest flexibility in performance, application range, and power consumption.

A 790 nW Low-Noise Instrumentation Amplifier for Bio-Sensing Based On Gm-RSC Structure

This paper presents a low-power low-noise instrumentation amplifier (IA) for bio-potential recording. The proposed IA is based on a novel Gm-RSC structure, whose gain is determined by the transconductance (Gm) and the equivalent resistance ([Formula: see text]) of the switched-capacitor (SC) load. The transconductance amplifier stage is based on the current-reuse telescope topology to achieve low noise at low-power dissipation. A resistor-controlled oscillator is designed to generate desirable operational frequency for SC load and to continuously tune the mid-band gain of the IA for different biomedical applications. Measurement results show that the input referred noise of the proposed IA is about 1.27[Formula: see text][Formula: see text]VRMS ([Formula: see text][Formula: see text]Hz) and the noise efficiency factor is 3.3. The range of tunable gain is from 28 to 40[Formula: see text]dB. The common mode rejection ratio and power supply rejection ratio at 50[Formula: see text]Hz are 72 and 78[Formula: see text]dB, respectively. The IA consumes only 660[Formula: see text]nA current at 1.2[Formula: see text]V supply and the active area of the IA is only 0.035[Formula: see text]mm2.

Low noise chopper-stabilized instrumentation amplifier with a ripple reduction loop

This paper presents a low noise and residual offset chopper-stabilized precision instrumentation amplifier intended for use in measurement systems. Conventional chopper-stabilized instrumentation a...

A Noise-Efficient 36 nV/ $\surd $ Hz Chopper Amplifier Using an Inverter-Based 0.2-V Supply Input Stage

This paper presents an analog front end (AFE) that achieves a high noise efficiency by using a chopper amplifier with a 0.2-V supply inverter-based input stage followed by a 0.8-V supply stage. The high input-stage current needed to reduce the input-referred noise is drawn from the 0.2-V supply, significantly reducing power consumption. The 0.8 V stage provides high gain and signal swing, improving linearity. Biasing and common-mode rejection techniques for the ultra-low-voltage stage are presented. The AFE is implemented in a 0.18 $\mu \text{m}$ CMOS process and integrates the chopper low-noise instrumentation amplifier, a programmable-gain amplifier, and an antialiasing filter. The AFE consumes 0.79 $\mu \text{W}$ and achieves a competitive power efficiency factor (PEF) of 1.6 and an input noise of 0.94 $\mu \text{V}_{\text {rms}}$ integrated from 0.5 to 670 Hz while maintaining a 36 nV/ $\surd $ Hz input noise density down to 0.5 Hz. The included 0.8/0.2-V buck converter may be used to provide the 0.2-V supply at 72%–74% efficiency without significantly increasing noise, yielding a PEF of 1.8.

A CMOS Fully Integrated 860-GHz Terahertz Sensor

This paper proposes a CMOS fully integrated 860-GHz terahertz (THz) sensor. The sensor integrates a single-NMOS THz detector, a low-noise chopper instrumentation amplifier and a high-resolution ΔΣ-ADC. The detector consists of a novel on-chip grounded patch antenna and a source-feeding NMOS field-effect transistor (FET) of the minimum size. A microstrip transmission line is designed to improve the power transfer efficiency between the antenna and the NMOS transistor. A notch filter is proposed to improve detector performance. To enable the theoretical analysis of the operation of the THz detector and the formulation of design guidelines, we propose a THz-FET device model in which a source-coupled FET for THz detection is modeled as a dc voltage source with a resistor. The model indicates that an FET with the minimum physical dimensions for a given CMOS process can produce the maximum output signal. The sensor is implemented in a 180-nm standard CMOS process. The detector achieves a voltage responsivity of 3.3 kV/W and an NEP of 106 pW/Hz1/2 at 860 GHz. The sensor noise and the readout circuit noise are 10.81 and 2.03 μ Vrms, respectively. The sensor obtains clear raster-scanning transmission images under continuous THz illumination.

A Dynamic Instrumentation Amplifier for Low-Power and Low-Noise Biopotential Acquisition

A low-power and low-noise dynamic instrumentation amplifier (IA) for biopotential acquisition is presented. A dynamic IA that can reduce power consumption with a timely piecewise power-gating method, and noise level with an alternating input and chopper stabilization technique is fabricated with a 0.13-μm CMOS. Using the reconfigurable architecture of the IA, various combinations of the low-noise schemes are investigated. The combination of power gating and chopper stabilization shows a lower noise performance than the combination of power gating and alternating input switching scheme. This dynamic IA achieved a power reduction level of 50% from 10 µA to 5 µA and a noise reduction of 90% from 9.1 µVrms to 0.92 µVrms with the combination of the power gating and chopper stabilization scheme.

A 0.5-V power-efficient low-noise CMOS instrumentation amplifier for wireless biosensor

This paper presents a low-power, low-noise CMOS instrumentation amplifier intended for use in wireless bio-potential monitoring system. It employs a capacitively-coupled topology to achieve high power efficiency. In order to depress the noise, chopper-stabilized technique is used and a transconductance-boost technique is introduced in low-noise amplifier (LNA). All MOS transistors implemented in LNA are biased in subthreshold region with a supply voltage of 0.5V to reduce the power consumption. Moreover, a DC-servo loop (DSL) is implemented to realize a high-pass corner for electrode offset cancellation. Implemented in a 0.18μm CMOS process, the front-end circuit occupies 0.48mm2 and draws 1.5μA. The capacitively-coupled chopper-stabilized instrumentation amplifier (CCIA) draws 800nA and its input-referred noise is 3.5μVrms integrated from 0.5 to 1kHz, which results in a NEF of 3.8 and a PEF of 7.2 respectively. The whole circuit achieves 98dB CMRR and 73dB PSRR. The total input-referred noise of the front-end instrumentation amplifier including the DSL is 4.3μVrms integrated from 0.5 to 1kHz.

A Portable Micro Gas Chromatography System for Lung Cancer Associated Volatile Organic Compound Detection

With the help of micro-electromechanical systems (MEMS) and complementary metal-oxide-semiconductor (CMOS) technology, a portable micro gas chromatography ( $\upmu {\text{GC}}$ ) system for lung cancer associated volatile organic compounds (VOCs) detection is realized for the first time. The system is composed of an MEMS preconcentrator, an MEMS separation column, and a CMOS system-on-chip (SoC). The preconcentrator provides a concentration ratio of 2170. The separation column can separate more than seven types of lung cancer associated VOCs. The SoC is fabricated by a TSMC $0.35\;\upmu {\text{m}}$ 2P4M process including the CMOS VOCs detector, sensor calibration circuit, low-noise chopper instrumentation amplifier (IA), 10 bit analog to digital converter, and the microcontrol unit (MCU). Experimental results show that the system is able to detect seven types of lung cancer associated VOCs (acetone, 2-butanone, benzene, heptane, toluene, m-xylene, 1,3,5-trimethylbenzene). The concentration linearity is ${{\text{R}}^{2}} = 0.985$ and the detection sensitivity is up to 15 ppb with 1,3,5-trimethylbenzene.

A low-noise instrumentation amplifier with DC suppression for recording ENG signals.

This paper presents an AC-coupled instrumentation amplifier for electroneurogram (ENG) activity recording. For this design, we evaluate gain and noise requirements based on interference sources (electrodes, power line, EMG). The circuit has been implemented in a commercially-available 0.35μm CMOS technology with total power consumption 460μW. The amplifier achieves CMRR 107 dB and integrated input referred noise 940 nV. The gain is 63 dB and the bandwidth is 0.5 Hz- 13 kHz. The chosen topology enables to minimise on-chip capacitance (only 27 pF), with a total chip area of 0.4mm2.