Low Noise Amplifier Circuit Research Articles

A self-biased GaN LNA with 30 dB gain and 21 dBm P1dB for 5G communications

Abstract We present a self-biased three-stage GaN-based monolithic microwave integrated circuit low-noise amplifier (LNA) operating between 26 and 29 GHz for 5G mobile communications. The self-biasing circuit, common-source topology with inductive source feedback, and RLC negative feedback loops between gate and drain of the third transistor were implemented to achieve low noise, good port match, high stability, high gain, and compact size. Measurement results show that the LNA has a high and flat gain of 30.5 ± 0.4 dB with noise figure (NF) of 1.65–1.8 dB across the band. The three-stage topology also achieves high linearity, providing the 1 dB compression point output power (P1dB) of 21 dBm in the band. To our knowledge, this combination of NF, gain, and linearity performance represents the state of art of self-biased LNA in this frequency band.

CNTFET Based Grounded Active Inductor for Broadband Applications

A new carbon nanotube field effect transistor (CNTFET) based grounded active inductor (GAI) circuit is presented in this work. The suggested GAI offers a tunable inductance with a very wide inductive bandwidth, high quality factor (QF) and low power dissipation. The tunability of the realized circuit is achieved through CNTFET based varactor. The proposed topology shows inductive behavior in the frequency range of 0.1–101 GHz and achieves to a maximum QF of 9125. The GAI operates at 0.7 V with 0.337 mW of power consumption. To demonstrate the performance of GAI, a broadband low noise amplifier (LNA) circuit is designed by utilizing the GAI based input matching-network. The realized LNA provides high frequency bandwidth (17.5–57 GHz), low noise figure (

Study on high power microwave nonlinear effects and degradation characteristics of C-band low noise amplifier

High power microwaves (HPM) coupled through the front door pose a potential threat to RF front ends, especially for low noise amplifiers (LNA). Therefore, A C-band LNA circuit model is constructed to investigate the non-linear effects and degradation characteristics of the LNA under HPM, and validate it against damaged samples analysis acquired in HPM injection experiment of LNA. The circuit model consists of a pseudocrystalline high electron mobility transistors (pHEMT) device equivalent physical model and other passive device SPICE models. The nonlinear relationship of input and output signals and the distribution of physical parameters of pHEMT device are analyzed by simulation. When the LNA injection power is less than a certain threshold, the nonlinear degradation of LNA is recoverable. However, when the LNA injection power is greater than a certain threshold, the pHEMT device in the circuit will be damaged by combustion. Under the influence of HPM, it forms a high current channel between gate and channel due to the avalanche breakdown of the Schottky junction and generates a hot spot on the side below the gate near the source, which will eventually cause burnout damage. Moreover, an empirical formula is presented to describe the relationship between the damage time of HPM and the injection power and energy. By scanning electron microscope (SEM) observation and energy dispersive spectrometer (EDS) analysis of the damaged samples, the results show that the pHEMT gate is vulnerable to HPM damage. The hot spot inside the pHEMT device in the simulation is consistent with the damage location of the LNA in HPM injection experiment.

PVT-compensated low voltage LNA based on variable current source for low power applications

In this paper, a new compensation technique for the low noise amplifier (LNA) with the high capability and efficiency for low power applications is proposed. The supply voltage and bias of the LNA are near the sub-threshold voltage, which has excellent effect on reducing power consumption. At this voltage level, the gain decreases and the various circuit parameters become extremely sensitive to process, voltage and temperature (PVT) changes. To overcome the problem, a compensating circuit with variable current source to control the LNA bias voltage is used. The output of the compensator circuit is adjusted according to changes in temperature, voltage and five process corners, and produces a variable voltage. The temperature compensator consists of two current sources that produce a current proportional to temperature changes. Regarding process and voltage compensator, according to the state created in the circuit, the appropriate amount of current is injected through the output and finally stabilizes the main parameters of the LNA circuit. In LNA circuit, for proper performance at supply voltage near the sub-threshold and attaining the gain improvement, forward body bias and gm-boosting techniques are employed, respectively. The LNA circuit along with the PVT compensator at supply voltage of 0.35 V, consumes about 567 µW power consumption that here 91 µW is caused by the PVT compensator circuit. In the proposed circuit, the rate of noise figure (NF) and gain (S21) changes compared to temperature changes in the five corners have decreased by 4.3 and 12.1 times versus LNA with constant bias, respectively. In this case, with 20% changes of VDD, NF and S21 changes decreased by 23 and 11.35 times, respectively. The results are provided by Cadence software using 65 nm CMOS technology.

A novel wide bandwidth FBSSIR integrated low noise amplifier for satellite navigational receiver system

This paper presents a Folded Butterfly Stub Stepped Impedance Resonator (FBSSIR) integrated low noise amplifier (LNA) implemented using packaging technology for the satellite navigation receiver system. By employing a novel structural deformation of a stepped-impedance-resonator (SIR), the proposed FBSSIR is achieved with a more compact structure, controllable transmission zero, adjustable center frequency, and adjustable bandwidth. The designed FBSSIR acts as a filter, and the input-output matching network is integrated into the proposed core LNA circuit. The Design-of-experiment (DoE) analysis is performed to analyze the passive component's sensitivity becoming desensitized, while statistical analysis is presented for the proposed FBSSIR integrated LNA to predict the percentage error tolerance. Its measurement result provides gain above 22 dB in the wide bandwidth from 1.6 GHz to 2.5 GHz, minimum NF of 2.7 dB at 1.8 GHz, which varies from 3 dB to 4.5 dB. The calculated area of FBSSIR integrated LNA is 10.7 × 2 cm2, while LNA is 3.3 × 1.6 cm2. It exhibits an input and output 1-dB compression point (IP1dB & OP1dB) of −23dBm and +2.3dBm.

Experimental investigation on the degradation of SiGe LNAs under different bias conditions induced by 3 MeV proton irradiation

The 3 MeV proton irradiation effects on SiGe low noise amplifier (LNA) (NXP BGU7005) performance under different voltage supply VCC (0 V, 2.5 V) conditions were firstly experimental studied in this present work. The S parameters including S11, S22, S21, 1 dB compression point and noise figure (NF) of the test samples under different bias voltage supply were measured and compared before and after 3 MeV proton irradiation. The total proton irradiation fluence was 1 × 1015 protons/cm2. The maximum degradation quantities of the gain S21 and NF of the test samples under zero bias are measured respectively 1.6 dB and 1.2 dB. Compared with the samples under 2.5 V bias supply, the maximum degradation of S21 and NF are respectively 1.1 dB and 0.8 dB in the whole frequency band. It is noteworthy that the gain and NF of SiGe LNAs under zero-bias mode suffer enhanced degradation compared with those under normal bias supply. The key influence factors are discussed based on the correlation of the SiGe device and the LNA circuit. Different process of the ionization damage and displacement damage under zero-bias and 2.5 V bias voltage supply contributed to the degradation difference. The underlying physical mechanisms are analyzed and investigated.

A 24GHz High Dynamic Range Low-Noise Amplifier Design Optimization Methodology and Circuit Configuration

A 24GHz High Dynamic Range Low-Noise Amplifier Design Optimization Methodology and Circuit Configuration

High frequency of low noise amplifier architecture for WiMAX application: A review

The low noise amplifier (LNA) circuit is exceptionally imperative as it promotes and initializes general execution performance and quality of the mobile communication system. LNA's design in radio frequency (R.F.) circuit requires the trade-off numerous imperative features' including gain, noise figure (N.F.), bandwidth, stability, sensitivity, power consumption, and complexity. Improvements to the LNA's overall performance should be made to fulfil the worldwide interoperability for microwave access (WiMAX) specifications' prerequisites. The development of front-end receiver, particularly the LNA, is genuinely pivotal for long-distance communications up to 50 km for a particular system with particular requirements. The LNA architecture has recently been designed to concentrate on a single transistor, cascode, or cascade constrained in gain, bandwidth, and noise figure.

An Enhanced Low Noise Amplifier Circuit at 6 GHz Center Frequency and NF Improvement in 180 nm CMOS Process

An Enhanced Low Noise Amplifier Circuit at 6 GHz Center Frequency and NF Improvement in 180 nm CMOS Process

Realization of LNA and Mixer Using CMOS 0.18μm Technology for 3.1 to 10.6 GHz

In this paper, low noise amplifier and mixer circuits are realized using 0.18μm CMOS technology in the frequency range of 3.1 to 10.6 GHz. LNA circuit uses the cascade topology with source degeneration technique, which help in reducing the non-linearity in the circuit. The current reuse topology is used to decrease the biasing voltage and hence to decrease the power consumption in the circuit. Realized circuit simulated in 0.18μm technology and various results shows highest gain S21 is 19.982dB and has the positive value in the entire frequency band, minimum NFmin is 1.270dB occurs at 1.27GHz and the highest NFmin is 3.4dB. S11 i.e. input reflection coefficient is -31.670dB and it is negative throughout the entire frequency range while the reflection at output port is report to be -7.449 dB. The resistive feedback topology helps in getting the flat gain in the frequency. Mixer circuit is also realize in 0.18μm CMOS technology, which uses current bleeding topology. Transformer help in converting the single ended signal into differential format. Maximum value of gain is 6.584dB, gain is positive in the entire RF frequency range, S11 i.e. the reflection at port1, which give the negative values in the entire frequency band, simulation of S12 i.e. leakage between the port 1 and 2 has negative values in the entire frequency band means proper isolation between the ports. The future work can the realization of the superheterodyne receiver in UWB band.

Design of High Performance Low-Noise Amplifier Circuit Based on Complementary Metal Oxide Semiconductor Technology

This paper designs a body-biased (BB) differential cascode low-noise amplifier (LNA) with current bias (CR) and capacitor cross-coupling (CCC) technology that meets the bandwidth requirements of 5 GHz wireless applications. In the design, the CCC technology in the differential cascode topology is used to effectively suppress the common mode noise, thereby improving the noise figure. The series resonant network eliminates parasitic capacitance at the input and output ends, thereby improving the power transmission efficiency. The CR technology formed by the intermediate capacitor shares the DC current input to the output device, thereby increasing the gain. This paper uses BB technology in the design to lower the threshold of the cascode device and improve the transconductance, which further improves the gain and reduces the power consumption. The CCC technology used in the paper improves linearity by eliminating the non-linear components present in the input device, which will not interfere with the transconductance of the output stage. This article has obtained excellent performance parameters including gain, noise figure (NF) and linearity without affecting the power consumption, integration and cost of the proposed design.

PVT ‐compensated low‐voltage and low‐power CMOS LNA for IoT applications

In this paper, a low‐noise amplifier (LNA) with process, voltage, and temperature (PVT) compensation for low power dissipation applications is designed. When supply voltage and LNA bias are close to the subthreshold, voltage has significant impact on power reduction. At this voltage level, the gain is reduced and various circuit parameters become highly sensitive to PVT variations. In the proposed LNA circuit, in order to enhance efficiency at low supply voltage, the cascade technique with gm boosting is used. To improve circuit performance when in the subthreshold area, the forward body bias technique is used. Also, a new PVT compensator is suggested to reduce sensitivity of different circuit's parameters to PVT changes. The suggested PVT compensator employs a current reference circuit with constant output regarding temperature and voltage variations. This circuit produces a constant current by subtracting two proportional to absolute temperature currents. At a supply voltage of 0.35 V, the total power consumption is 585 μW. In different process corners, in the proposed LNA with PVT compensator, gain and noise figure (NF) variations are reduced 10.3 and 4.6 times, respectively, compared to a conventional LNA with constant bias. With a 20% deviation in the supply voltage, the gain and noise NF variations decrease 6.5 and 34 times, respectively.

Performance Assessment of CMOS circuits using III-V on Insulator MOS Transistors

In this work, with the help of extensive technology computer-aided design simulations, we report a comprehensive study of MOSFET based circuit design using ultra-thin body III-V on-insulator (OI) CMOS transistors. We demonstrate the circuit performance of III-V CMOS by combining InAs-OI n-channel and GaAs-OI junction-less p-channel transistors. The performance metrics of different circuits designed using III-V transistors are also compared with III-V/Germanium and Silicon-on-insulator (SOI) based CMOS logic. CMOS inverter circuit designed using III-V/Ge (InAs-OI/GeOI) CMOS shows 51% and 17% reduction in rise and fall time compared to SOI CMOS. The oscillation frequency of the ring oscillator designed using III-V/Ge (InAs-OI/GeOI) and III-V (InAs-OI/GaAs-OI) CMOS logic is approximately three times and two times higher than SOI based design. The unity-gain bandwidth of the inverting amplifier using III-V/Ge (InAs-OI/GeOI) and III-V (InAs-OI/GaAs-OI) architecture is 22 times and 9.5 times higher compared to SOI CMOS based circuit. Static noise margin (SNM) of conventional six-transistor (6-T) SRAM cell is also analyzed during hold operation. Due to the poor electrostatic integrity of III-V transistors, degradation in SNM is observed compared to its SOI counterparts. The cascode low noise amplifier (LNA) circuit designed using InAs-OI transistor shows the higher gain and low noise figure at the same operating frequency compared to the SOI transistor-based LNA.

A 28 GHz LNA Circuit Layout Debug through Electromagnetic Analysis

This paper presents the debug process of a 28[Formula: see text]GHz low noise amplifier (LNA) circuit layout. This study is guided utilizing an electromagnetic (EM) simulation program where inductive coupling, the parasitics of dc voltage line and ground line are extracted and simulated, their impacts on LNA performance are also quantitatively characterized. For validation, the circuit was designed and fabricated using GF8HP 0.13[Formula: see text]um SiGe BiCMOS process. The measurement shows that the gain S21 is 23.22[Formula: see text]dB, S11 and S22 are [Formula: see text] and [Formula: see text][Formula: see text]dB, respectively, and the noise figure is 4.26[Formula: see text]dB. The power consumption is 14.25[Formula: see text]mW, the chip area including pads is 540[Formula: see text][Formula: see text][Formula: see text]um.

Design of 130nm RFCMOS differential low noise amplifier

<span>In this paper, an inductively degenerated CMOS differential low noise amplifier circuit topology is presented. This low noise amplifier is intended to be used for wireless LAN application. The differential low noise amplifier proposed provide high gain, low noise and large superior out of band IIP3. The LNA is designed in 130 nm CMOS technology. Simulated results of gain and NF at 2.4GHz are 20.46 dB and 2.59 dB, respectively. While the simulated S<sub>11</sub> and S<sub>22</sub> are −11.18 dB and −9.49 dB, respectively. The IIP3 is −9.05 dBm. The LNA consumes 3.4 mW power from 1.2V supply. </span>

Optimal Design of Ultra-Low-Power 2.4 GHz LNA for IEEE 802.15.4/Bluetooth Applications

In this paper, an evolutionary computation-based optimal design of low power, high gain inductive source degenerated CMOS cascode low noise amplifier (LNA) circuit is presented for 2.4[Formula: see text]GHz frequency. The main challenge for the design of radio frequency (RF) LNAs at nanometer range is the thermal noise generated in the short-channel MOSFETs. The short-channel effects (SCEs), such as velocity saturation and channel-length modulation, are considered for the design of CMOS LNA. The evolutionary algorithm taken for this work is Moth-Flame Optimization (MFO) algorithm. MFO is utilized for the optimization of noise figure (NF) while satisfying all the other design performance parameters like gain, matching parameters at input/output, power dissipation, linearity, stability. Optimal values of the sizes of the transistors and other design parameters in designing the LNA circuit are also obtained from the MFO algorithm. The CMOS LNA circuit is designed by using MFO-based optimal design parameters in CADENCE software with a standard 0.18[Formula: see text][Formula: see text]m CMOS process. The designed LNA shows a gain of 15.28[Formula: see text]dB, NF of 0.376[Formula: see text]dB, the power dissipation of 936[Formula: see text][Formula: see text]W and IIP3 of [Formula: see text][Formula: see text]dBm at 2.4[Formula: see text]GHz. The designed LNA achieves better trade-off which results in an FOM of 42.3[Formula: see text]mW[Formula: see text] and may be useful in the receiver module of IEEE 802.15.4 for WLAN applications.

Design and Analysis of 2.4 GHz Low-Noise, High-Gain 0.18 μm CMOS Cascode Low-Noise Amplifier for IRNSS Applications

Low-Noise Amplifier (LNA) plays a crucial part in Radio Frequency (RF) front-end architecture. This paper mainly focuses on designing LNA for Indian Regional Navigation Satellite System (IRNSS) receiver. IRNSS operates on two frequency bands (L5 and S band) and this design is proposed for S band with the center frequency of 2492.028 MHz. Cascode topologies are considered to be conventional ones and they provide higher gain and better reverse isolation. Four different approaches of single-stage cascode topology, such as Common Source (CS) cascode, Common Gate (CG) cascode, shunt-resistive feedback cascode and current reuse cascode, were designed and their performance metrics, based on gain, Noise Figure (NF), return losses and stability, are presented. Focused on the gain and noise figure improvements, Common Source (CS) cascode with interstage series LC circuit LNA was designed and optimized with input and output matching circuitries. The proposed optimized circuit uses current reuse technique along with CS stage to improve the power gain and to achieve low-noise figure. The interstage LC circuit is mainly implemented to act as a tuning circuit to achieve a narrow range of frequency. The proposed work is simulated using 180 nm CMOS technology Generic Process Design Kit (GPDK) and achieve a power gain (S21) of 24.89, 0.994 dB NF, −16.2 dB input return loss (S11) and −11.06 dB output return loss (S22), with higher reverse isolation around −30.47 dB at 1.8 V power supply.

Analysis and design of low‐power and high‐gain complementary metal oxide semi‐conductor low noise amplifier operating at 28 GHz frequency for millimeter wave LEOS, local multiport distribution system and radar application

AbstractLow‐noise amplifier supports broadband standards with the advantage of low‐power, high‐gain, and low noise figure (NF). The low‐frequency design of this low‐noise amplifier (LNA) is used for multistandard wireless applications and the high‐frequency design of this LNA can be used in millimeter wave radar applications. This LNA is designed at the front‐end for amplification in the receiver side, so that signal to noise is adjusted on the multistandard receivers. LNA permits performance of the design with various parameters like NF, power efficiency, gain of the LNA, figure of merits, and linearity of the low‐noise amplifier. In 28 GHz, millimeter wave (mmW) circuits' design and analysis with high gain, low power, low NF, and wide bandwidth are preferred for radio frequency front end. This paper discusses, the Cascode design of CMOS LNA circuit at 28 GHz, and the novelty of the design is that it can operate at two different set of frequency bands (21 and 28 GHz) and it is multiband and multitunable. The design's conversion gain (S21) of 17.4 dB, NF of 4 dB, stability of 1, power optimized to 22.3 mW, and area of 0.399mm2 are reported. The input and output reflection coefficients are S11 ≤ −10 dB and S22 ≤ −10 dB. Electromagnetic simulation is performed using advanced design system tool. Output power of the proposed design is 2 dBm, transition frequency (fT) is 64GHz, and maximum operating frequency (fmax) is 96GHz. The observed results show that the proposed CMOS LNA design finds its suitability in mmW cloud radar application of mono‐pulse radar system and radar front‐end receiver circuits.

IMPROVED PERFORMANCE OF LNA USING HIGH QUALITY FACTOR PGS ON-CHIP SPIRAL INDUCTORS

This paper presents a detailed study of on-chip spiral inductors with patterned ground shield (PGS) inserted between the spiral inductorand the silicon substrate. This new design has been implemented in source degeneration cascode lownoise amplifier (LNA) circuit to show how the PGS inductors improve the performance of the circuit. An operation in 1.8V supply voltage, source degeneration cascode LNA structure was studied with both technology and PGS inductors. In this paper, the Agilent ADS (Advanced Design System) simulation software and TSMC 0.18μm CMOS process parameters were adopted to achieve the low-cost characteristics and high integration to fit the performance of 2.4 GHz LNA design under IEEE 802.11a specification.According to the co-simulation results, the forward gain (S21) improved from 13.432 to 21.474 dB, and the (S12)is below the typical value of -15dB. The input impedance (S11) and the output impedance (S22) also represented good performance. In addition, the minimum noise figure was quite good. Thus, the LNA circuit with PGS inductorswas better in the availability and the possibility of 802.11a specification.

Design of C-band Low-noise Amplifier (LNA) Using E-pHEMT Device for Satellite Communication System

A low-noise amplifier (LNA) plays an indispensable role in a communication system for amplification purposes at the transceiver. LNA design in radio frequency (RF) circuits involve various key attributes, namely noise figure (NF), gain, and power consumption. This paper focuses on the design of a C-band LNA for satellite communication system with a centre frequency of 6 GHz using ATF-55143 enhancement-mode pseudomorphic high-electron-mobility transistor (E-pHEMT) technology. The LNA performance is augmented by adding inductors to the drain and gate of the ATF-55143 transistor. Smith chart impedance matching technique is implemented to foster a more precise matching for input and output of the LNA. In this work, the C-band LNA is biased at VDS of 2.7 V and IDS of 10 mA. Electromagnetic (EM) software is used to design and simulate the performance of the LNA circuit layout. Simulation results indicate NF of 2.66 dB and power gain (S21) of 12.29 dB. The LNA consumes 27 mW from a 3 V DC supply.