Abstract
This paper presents the debug process of a 28[Formula: see text]GHz low noise amplifier (LNA) circuit layout. This study is guided utilizing an electromagnetic (EM) simulation program where inductive coupling, the parasitics of dc voltage line and ground line are extracted and simulated, their impacts on LNA performance are also quantitatively characterized. For validation, the circuit was designed and fabricated using GF8HP 0.13[Formula: see text]um SiGe BiCMOS process. The measurement shows that the gain S21 is 23.22[Formula: see text]dB, S11 and S22 are [Formula: see text] and [Formula: see text][Formula: see text]dB, respectively, and the noise figure is 4.26[Formula: see text]dB. The power consumption is 14.25[Formula: see text]mW, the chip area including pads is 540[Formula: see text][Formula: see text][Formula: see text]um.
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