Low Gate Bias Research Articles

Fabrication and characteristics of Ag/Pb(Zr0.53Ti0.47)O3/ultrathin-SiO2/Si and Ag/Pb(Zr0.53Ti0.47)O3/YBa2Cu3O7.δ systems

The Ag/Pb(Zr0.53Ti0.47)O3 (PZT) /YBa2Cu3O7.δ (YBCO) with small gate area and Ag/PZT/ultrathin-SiO2/Si heterostructrual devices have been prepared. The polarization and field effect characteristics have been studied. Highly (100) oriented PZT was successfully integrated onto Si using ultrathin-SiO2 buffer layer. Obvious field effect occurred at a low gate bias of 0.5 V. In Ag/PZT/YBCO three terminal device with the small gate area of 6×10−6 cm2, very large saturation and remnant polarization and small coercive field are obtained. The maximum modulation of YBCO channel resistance ΔRDS/RDS is 3% under the gate voltage of±9 V at 64 K, at which the superconducting and normal state transition is driven by channel current.

Comparative study of self-aligned and nonself-aligned SiGe p-metal–oxide–semiconductor modulation-doped field effect transistors with nanometer gate lengths

A self-aligned process used to fabricate p-type SiGe metal–oxide–semiconductor modulation-doped field effect transistors (MOS-MODFET) is described. Self- and nonself-aligned p-type Si0.2Ge0.8/Si0.7Ge0.3 MOS-MODFETs with gate-lengths from 1 μm down to 100 nm were fabricated. The dc and microwave characteristics of these devices are presented. In comparison with nonself-aligned devices, self-aligned devices exhibited higher extrinsic transconductances, lower threshold voltages, higher unity current gain cutoff frequencies fT, and maximum oscillation frequencies fMAX. Self-aligned MOS-MODFETs with a gate length of 100 nm exhibited an extrinsic transconductance of 320 mS/mm, an fT of 64 GHz, and an fMAX of 77 GHz. To our knowledge, these are the highest data ever reported for any MOS-type p-FETs with a SiGe channel. All these excellent performances were measured at very low drain and gate biases.

Reduction of stress-induced leakage currents in thin oxides by application of a low post-stress gate bias

We have observed that stress-induced leakage currents (SILC) in thin gate oxides (4.5 nm) could be reduced by applying a low gate bias to the oxides after stress, regardless of the polarity of the applied gate bias. The reduction of SILC increased with the applied gate bias and began to saturate after 105 s. In addition, the reduction of SILC was significantly enhanced in a hydrogen ambient, suggesting a strong link between the reduction of SILC and trapped-hole annealing.

Design, fabrication, and analysis of SiGeC heterojunction PMOSFETs

We present the evaluation of the strain-stabilizing capabilities of C in the Si/sub 1-x/Ge/sub x/ system. To demonstrate these effects, we have designed Si/sub 1-x-y/Ge/sub x/C/sub y/ heterojunction PMOSFET devices over a range of Ge concentrations, with thicknesses that would typically result in related or metastable films under normal processing conditions. The dc characteristics of Si/sub 1-x-y/Ge/sub x/C/sub y/, SiCe, and Si PMOSFETs (L=10 /spl mu/m) were evaluated at room temperature and at 77 K. In general, the saturation mobility in Si/sub 1-x-y/Ge/sub x/C/sub y/ devices is higher than that of Si/sub 1-x/Ge/sub x/ and Si devices at low gate bias and room temperature. This enhancement is attributed to the strain stabilization effect of C. With proper optimization of Ge and C concentrations, it is possible to fabricate devices with significant improvements in drive current under normal operating conditions (0-3 V, 300 K). This application of Si/sub 1-x-y/Ge/sub x/C/sub y/ in PMOSFETs demonstrates the potential benefits of using of C in the Column IV heterostructure system.

Low frequency noise measurements of p-channel Si/sub 1-x/Ge/sub x/ MOSFET's

In this brief, we report an investigation of the low frequency noise in p-channel SiGe MOSFET's. At low gate bias the noise spectrum consists of several trap related generation-recombination (g-r) noise components. At higher gate bias, the noise spectrum is dominated by 1/f noise. The 1/f noise is attributed to a fluctuation in the number of free carriers and the effective slow state trap density at the Fermi energy calculated.

Temperature dependence of hot carrier induced MOSFET degradation at low gate bias

Abstract This paper reports a new experimental finding on the temperature dependence of the substrate current and hot carrier induced device degradation at low gate bias. It has been found that the substrate current increases and the drain current degradation is more significant for high operating temperature at low gate bias. It has been observed that the hot carrier induced performance degradation of a latch-type input buffer increases at the elevated temperature.

Heterostructure P-channel metal–oxide–semiconductor transistor utilizing a Si1−x−yGexCy channel

The dc characteristics of Si1−x−yGexCy P-channel metal–oxide–semiconductor field-effect transistors (PMOSFETs) were evaluated between room temperature and 77 K and were compared to those of Si and Si1−xGex PMOSFETs. The low-field effective mobility in Si1−x−yGexCy devices is found to be higher than that of Si1−xGex (grown in the metastable regime) and Si devices at low gate bias and room temperature. However, with increasing transverse fields and with decreasing temperatures, Si1−x−yGexCy devices show degraded performance. The enhancement at low gate bias is attributed to the strain stabilization effect of C. This application of Si1−x−yGexCy in PMOSFETs demonstrates potential benefits in the use of C for strain stabilization of the binary alloy.

Distinct two-dimensional carrier injection phenomena in extremely thin-SOI insulated-gate pn-junction devices: prospect of new device applications

This paper describes two-dimensionally confined carrier-injection phenomena in thin-SOI insulated-gate pn-junction devices fabricated on SIMOX substrates. At 28 K, the conductance shows step-like anomalies due to the manifestation of a two-dimensional subband system in an 8-nm-thick-SOI structure at a low gate bias. Conductance shows an oscillation-like feature at a high-gate bias because of the change in injection mode. These effects are examined by theoretical simulations based on quantum mechanics. Furthermore, the discussion addresses the prospect of a new device application, such as a surface tunnel transistor.

Modifications of Fowler-Nordheim injection characteristics in /spl gamma/ irradiated MOS devices

In this work we have investigated how gamma irradiation affects the tunneling conduction mechanism of a 20 nm thick oxide in MOS capacitors. The radiation induced positive charge is rapidly compensated by the injected electrons, and does not impact the gate current under positive injection after the first current-voltage measurement. Only a transient stress induced leakage current at low gate bias is observed. Instead, a radiation induced negative charge has been observed near the polysilicon gate, which enhances the gate voltage needed for Fowler-Nordheim conduction at negative gate bias. No time decay of this charge has been observed. Such charges slightly modify the trapping kinetic of negative charge during subsequent electrical stresses performed at constant current condition.

Low-frequency noise characteristics of hot carrier-stressed buried-channel pMOSFETs

Prestress and poststress low-frequency noise characteristics of buried-channel LDD pMOSFETs have been studied. The devices were stressed at low gate and high drain bias, and the poststress drain current increases due to the hot-electron induced channel shortening effect. The noise measurements were carried out between 10 Hz and 100 kHz, 1/ f 1.2 and generation–recombination current noises have been found in the drain current noises. The poststress 1/ f 1.2 drain current noise increases in both the linear and saturation regime. This behavior is attributed to the increase of interface states and oxide electron charges after stress.

A unified model for the self-limiting hot-carrier degradation in LDD n-MOSFETs

A new insight into the self-limiting hot-carrier degradation in lightly-doped drain (LDD) n-MOSFETs is presented. The proposed model is based on the charge pumping (CP) measurement. By progressively lowering the gate base level, the channel accumulation layer is caused to advance into the LDD gate-drain overlap and spacer oxide regions, extending the interface that can be probed. This forms the basis of a novel technique, that allows the contributions to the CP current, due to stress-induced interface states in the respective regions, to be effectively separated. Results show that interface state generation initiates in the spacer oxide region and progresses rapidly into the overlap/channel region with stress time. The close correspondence between the linear drain current degradation, measured at high and low gate bias, and the respective interface state generation in the spacer and the overlap/channel regions deduced from CP data, provides an unambiguous experimental evidence that the degradation proceeds in a two-stage mechanism, involving first a series resistance increase and saturation, followed by a carrier mobility reduction. The saturation in series resistance increase results directly from a reduced interface state generation rate in the spacer oxide. For a given density of defect precursors and considering an almost constant channel field distribution near the drain region during stress, interface trap generation rate is shown to exhibit an exponential stress time dependence, with a characteristic time constant determined by the applied voltages. This observation leads to a lifetime extrapolation methodology. Lifetime due to a particular stress drain voltage V/sub d/, may be extracted from a single composite degradation characteristic, obtained by shifting characteristics for various stress V/sub d/'s, along the stress time axis, until the characteristics merge into a single curve.

Compression in transconductance at low gate voltages in submicron GaAs metal semiconductor field-effect transistors

In submicron GaAs metal semiconductor field-effect transistors, the shift in the transconductance (gm) peak towards the high negative gate voltage end is often observed. Factors causing this abnormality were investigated. It is believed that if the surface potential and the Schottky barrier potential are of the same order of magnitude then there will be a strong probability that the peak gm value will appear at high negative gate voltages rather than near zero gate bias. It was shown that under these circumstances the drain current at low gate biases is not under the direct influence of gate depletion but rather is controlled by surface depletion in the gate-drain gap. At high negative gate voltages, depletion under the gate has the dominant effect on channel current, and the device exhibits an improved performance. Recessed gate technology is thought to be a solution to eliminate the surface state effects of a free drain-source surface. It was shown that a simple gate recess will not eliminate the possibility of gm compression and shift unless the Schottky barrier potential is greater than the free-surface potential.

The gate bias and geometry dependence of random telegraph signal amplitudes [MOSFET

A new random telegraph signal (RTS) amplitude model based upon band bending fluctuations has been developed, in contrast to other studies of RTS noise amplitudes, which are derived from RTS fitting parameters, it is demonstrated in this work that noise amplitudes may be predicted from band bending calculations and device DC characteristics. This new model suggests that the decrease in band bending associated with slow-state trapping results in mobility degradation for low gate biases (Coulombic-scattering-limited) and an enhancement in mobility due to vertical field reductions at high gate biases (surface roughness/phonon scattering limited). The band bending formulation shows good correlation with experimental data and accurately predicts the observed dependence upon effective channel length and width.

A new assessment of the self-limiting hot-carrier degradation in LDD NMOSFET's by charge pumping measurement

By progressively lowering the gate-base level in the charge pumping (CP) measurement, the channel accumulation layer is caused to advance into the LDD gate-drain overlap and spacer-oxide regions, extending the interface that can be probed. This constitutes the basis of a new technique that separates the hot-carrier-induced interface states in the respective regions. Linear drain current degradation, measured at low and high gate bias, provides clear evidence that interface state generation initiates in the spacer region and progresses rapidly into the overlap/channel regions with stress time in a two-stage mechanism, involving first a series resistance increase and saturation, followed by a carrier mobility reduction.

Partial breakdown of the tunnel oxide in floating gate devices

The reliability of thin oxide used for charge tunneling in the erase/program operation of floating gate devices, e.g. EEPROM, is examined. It is frequently observed in the simulated Erase operation that the oxide can break down partially, which implies localized physical damage and oxide thinning at and/or near the anode, i.e. the interface, before a complete breakdown occurs. After the partial breakdown, the negative-gate-biased Fowler-Nordheim tunneling current essentially arises at a lower gate bias, with the shifted amount depending on the degree of oxide thinning. In contrast, the positive-gate-biased characteristic exhibits a more drastic change, usually similar to an electric short, obviously due to the combining effect of field enhancement, lower barrier and high density of charge traps near the damaged site.

Field-Effect Conductance Activation Energy in Polycrystalline Silicon Thin-Film Transistors after Bias Stress

We have bias-stressed hydrogen-passivated polycrystalline silicon thin-film transistors by varying the bias condition and have measured the change in the field-effect conductance activation energy as a result of the bias stress. For stress by a high gate bias voltage, a slight broadening occurs in the activation energy curve, while stress by a low gate bias voltage gives rise to a shoulder. Numerical calculation shows that the change in activation energy is due to defect generation in the poly-Si layer and for stress by low gate voltage, defects are localized near the drain region. The energy distribution of defects cannot be obtained accurately, but its position is higher than 0.2 eV above midgap.

Two-dimensionally confined injection phenomena at low temperatures in sub-10-nm-thick SOI insulated-gate p-n-junction devices

This paper describes two-dimensionally confined carrier injection phenomena in thin-SOI insulated-gate pn-junction devices fabricated on SIMOX substrates. At 28 K conductance shows step-like anomalies due to the manifestation of a two-dimensional subband system in an 8-nm-thick-SOI structure at a low gate bias. Conductance shows an oscillation-like feature at a high gate bias because of the injection mode change. These effects are examined by theoretical simulations based on quantum mechanics.

Choking of electron flow: A mechanism of current saturation in field-effect transistors

We describe a mechanism of the current saturation in a field-effect transistor (FET) caused by choking of electron flow. The choking occurs when the electron velocity at the drain side of the channel reaches the plasma-wave velocity. This effect is quite similar to the choking of a gas flow in a pipe. This mechanism is an alternative to the well-known mechanism of current saturation caused by the drift velocity saturation in the FET channel. We show that the choking mechanism may dominate in a submicrometer ${\mathrm{Al}}_{\mathit{x}}$${\mathrm{Ga}}_{1\mathrm{\ensuremath{-}}\mathit{x}}$As/GaAs FET at 10 K and low drain and gate bias voltages.

Evaluation of hot-carrier degradation of n-channel MOSFETs at low gate bias

Hot-carrier effects pose a significant reliability issue as device dimensions are scaled down [1]. The ability to accurately predict hot-carrier lifetimes for devices is important for the development of fine-geometry MOS technology [2]. The hot-carrier degradation model developed by Hu et al. [1] at the University of Berkeley is widely used to predict device lifetimes under normal operating conditions from the results of accelerated tests. This model predicts device lifetimes at all bias conditions, while older models predict only worst case lifetimes at given drain voltages [3]. The Berkeley model is thus applicable to circuit-level reliability simulations. However, this paper shows that the model exaggerates the dependence of lifetime on gate bias, leading to very pessimistic minimum lifetime predictions. Since hot-carrier reliability is a crucial factor in modern MOS technologies, this error in the model may lead to mistaken conclusions on product viability.

Effects of plasma charging damage on the noise performance of thin-oxide MOSFET's

The effects of plasma charging damage on the noise properties of MOSFET's which is a necessary consideration for high-performance analog applications were studied using 1/f noise, Random Telegraph Signal (RTS) noise and charge pumping techniques. Plasma ashing significantly increases the drain flicker noise, more with larger antenna sizes, mainly in the low-frequency and low-gate-bias regime. The observed RTS reveals that an oxide trap with a few milliseconds time constant was induced by the plasma processing. This oxide trap is located in the energy space which corresponds to the low gate bias of device. This trap may be reproduced by Fowler Nordheim stress as suggested by noise and charge pumping measurements, supporting the notion that plasma ashing damage is a result of electrical stress, not radiation, for example.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>