Low Drain Voltage Research Articles

High-performance Ge/GaAs heterojunction tunneling FET with a channel engineering for sub-0.5 V operation

A Ge/GaAs heterojunction provides momentous improvements in current characteristics due to its band arrangement and enhanced band-to-band tunneling. Ge has a narrow bandgap (0.67 eV) and a smaller electron affinity (4.0 eV) and GaAs has a relatively larger energy bandgap (1.42 eV) and electron affinity (4.07 eV) at room temperature. For the heterojunction of GaAs and Ge, by grafting p+ Ge source and n+ GaAs well in forming a GaAs-on-Ge structure, prominently high performances including current drivability of Ion = 482.6 μA μm−1, current ratio (Ion/Ioff) = 1.76 × 109, and S = 8.02 mV dec−1 have been achieved by design optimization of doping profile aiming at extremely low drain voltage (VDS) of 0.3 V. The design variables were VDS, the length of n+ doped well in the GaAs layer (Lwell) and n-type doping concentration in the drain junction (Ndrain). They are confirmed by the results that Ge/GaAs heterojunction TFET is very suitable for low-power and high-speed applications.

Simulations of Transient Behavior and Parasitic Effects for 20 nm Gate Length of PD SOI nMOSFET

In this paper, we report the possible transient behavior for 20nm partially depleted silicon-on-insulator (PD SOI) n-channel MOSFET studied using Synopsys TCAD program. Tunnelling model is set at Si/SiO2 interface by varying front gate oxide. Parasitic floating body effects also have been observed in the device behavior for both linear and saturation regions, the magnitude of these effects depends on the front gate oxide thickness. For 4nm gate oxide thickness, the parasitic floating body effect is dominant at low drain voltage.

Contact Effects in Organic Thin Film Transistors with Different Device Structures

The electrical characteristics of organic thin film transistors (OTFTs) are frequently affected by contact effects, which can seriously reduce the transistor performance. The “parasitic” voltage drop at the contacts, induced by contact resistance, decreases the effective drain-source and gate-source voltages applied to the intrinsic channel of the transistor, reducing the device current. The importance of the contact resistance, Rc, is more relevant in the case of high carrier mobility and/or small channel length devices, where its value may become comparable or even larger than the channel resistance. Rc appears to be strongly affected by the device architecture and much higher Rc-values are typically observed, at low drain voltages, in coplanar structures (i.e. Bottom Gate/Bottom Contact, BGBC devices) than in staggered structures (i.e. Top Gate/Bottom Contact, TGBC devices). The presence of Schottky barriers, trap states, field dependence of carrier mobility and defected regions near the electrodes have been suggested as the origin of Rc.In this work, the contacts effects in devices with different architectures (staggered and coplanar) will be discussed. Devices characteristics have been measured at different temperature and the results have been analysed by using 2D numerical simulations (fig. 1 and 2). The electrical characteristics of both type of devices can be reproduced considering a Schottky barrier at the source contact with an “effective” barrier lowering, that takes into account different field-dependent effects occurring at the contacts (Shottky effect, tunnelling, trap assisted tunneling) that can increase the current injected by the electrode (fig.1 and 2). In the case of staggered devices, the detailed analysis of the current density shows that, at low Vds and for a given Vgs, the current is mainly injected from an extended source contact region overlapped by the gate electrode, inducing a current spreading along the contact (Ic - current in fig.3). The distribution of the current spreading remains basically constant for increasing Vds up to a value Vdsat1 (fig. 1), when the depletion layer of the Schottky contact expands reaching the insulator-semiconductor interface and causing the pinch-off of the channel at the source end. For Vds>Vdsat1 the current injected from the edge of the source contact rapidly increases (Iedge in fig.3a), due to field enhanced injection mechanisms, while the current injected from the remaining part of the source contact basically saturates. At higher drain voltage (Vds>Vdsat2, see fig.1), pinch off at the drain occurs. In the case of coplanar devices, current spreading, obviously, does not occurs and even at low Vds the current increase is related to the field enhanced injection mechanisms that take place at the edge of the source contact (fig.3b). The lack of the extended contact contribution to the injected current explains the higher contact resistance usually observe in coplanar devices at low Vds compared to staggered OTFTs. On the other hand, at high Vds (saturation condition) higher electric fields are present, in coplanar structure, near the source, that is in direct contact to the channel region. This results in a more efficient carrier injection that allows obtaining an almost ohmic contact condition in coplanar devices in saturation condition.

HCS degradation of 5 nm oxide high-voltage PLDMOS

Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage (VGS) and high drain voltage (VDS), reduction of the ON-resistance (RON) is observed. At stress times at which RON almost reaches its constant level, an increase of the drain leakage in OFF state (VDS=−60V, VGS=0V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25nm gate oxide thickness, the threshold voltage of 5nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS.

A Statistical Model for the Headed and Tail Distributions of Random Telegraph Signal Magnitudes in Nanoscale MOSFETs

Trapping-detrapping of a single electron via an individual trap in metal-oxide–semiconductor field-effect transistor (MOSFET) gate dielectric constitutes two-level random telegraph signals. Recent 3-D technology computer-aided design (TCAD) simulations, on an individual MOSFET, revealed that with the position of the trap as a random variable, resulting random telegraph signals relative magnitude <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">\(\Delta I_{{\boldsymbol {{d}}}}/I_{{\boldsymbol {{d}}}}\) </tex-math></inline-formula> in the subthreshold current at low drain voltage can have two distinct distributions: a headed one for a percolation-free channel and a tail one for a percolative channel. The latter may be effectively treated by a literature formula: ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">\(\Delta I_{{\boldsymbol {{d}}}}/I_{{\boldsymbol {{d}}}})=(I_{\mathbf {loc}}/I_{{\boldsymbol {{d}}}})^{\mathrm {\mathbf {2}}}\) </tex-math></inline-formula> , where <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">\(I_{\mathbf {loc}}\) </tex-math></inline-formula> is the local current around the trap. In this paper, we show how to make this formula practically useful. First, we conduct 3-D TCAD simulations on a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">\(35\times 35\) </tex-math></inline-formula> -nm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">\(^{\mathrm {\mathbf {2}}}\) </tex-math></inline-formula> channel to provide <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">\(\Delta I_{{\boldsymbol {{d}}}}/I_{{\boldsymbol {{d}}}}\) </tex-math></inline-formula> for a few positions of the trap. This leads to a new statistical model in closed form, which can reproduce headed distributions. Straightforwardly, key criteria are drawn from the model, which can act as guidelines for the adequate use of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">\(I_{\mathbf {loc}}/I_{{\boldsymbol {{d}}}}\) </tex-math></inline-formula> formula. Extension to threshold voltage shift counterparts, from subthreshold through transition to inversion, is successfully achieved. Importantly, use of the model may overcome the drawbacks of the statistical experiment or simulation in the field.

Low Phase Noise GaN HEMT Oscillators With Excellent Figures of Merit

This letter presents guidelines for the design of low phase noise oscillators in GaN high electron mobility transistor (HEMT) technology. The design starts from bias-dependent low-frequency (LF) noise measurements. Oscillator topology and bias point are then chosen for operation in regions where LF noise is low. The best LF noise properties are obtained for low drain voltage and current. Thus, the low phase noise can be achieved at low dc power which also means that power normalized phase noise figure of merit (FOM) will be good.

Analysis of channel electrons scattered in each region of silicon nanodiode at low drain voltage using nonequilibrium Green’s function approach

We analyzed channel electrons caused by scattering on the drain current of a silicon nanodiode. Electrons in the channel region are classified by the scattering positions: the source, channel, and drain regions. We focused our attention on the operation in a low-voltage range to study ultralow-power operation. To analyze electron transport in the device, we employed the nonequilibrium Green’s function (NEGF) approach, which takes a complete quantum effect into consideration. It was found that channel electrons backscattered from the drain region cause a negative drain current when the drain voltage decreases. However, scattered channel electrons contribute only slightly to the drain current owing to the presence of substantial ballistic channel electrons, although the average velocity of scattered channel electrons is as large as that of ballistic channel electrons in a low-drain-voltage range. This result is beneficial for the development of future ultralow-power devices.

Strained silicon based complementary tunnel-FETs: Steep slope switches for energy efficient electronics

Electrical characteristics of silicon nanowire tunnel field effect transistors (TFETs) are presented and benchmarked versus other concepts. Particular emphasis is placed on the band to band tunneling (BTBT) junctions, the functional core of the device. Dopant segregation from ion implanted ultrathin silicide contacts is proved as a viable method to achieve steep tunneling junctions. This reduces defect generation by direct implantation into the junction and thus minimizes the risk of trap assisted tunneling. The method is applied to strained silicon, specifically to nanowire array transistors, enabling the realization of n-type and p-type TFETs with fairly high currents and complementary TFET inverters with sharp transitions and good static gain, even at very low drain voltages of VDD=0.2V. These achievements suggest a considerable potential of TFETs for ultralow power applications. Gate-all-around Si nanowire array p-type TFETs have been fabricated to demonstrate the impact of electrostatic control on the device performance. A high on-current of 78μA/μm at VD=VG=1.1V is obtained.

Band structure effect on the electron current oscillation in ultra-scaled GaSb Schottky MOSFET: tight-binding approach

This paper explores band structure effect on the quantum transport of a low-dimensional GaSb Schottky MOSFET (SBFET) for the implementation of III---V transistor with a low series resistance. Precise treatment of the full band structure is employed applying sp 3 d 5 s ∗ tight-binding (TB) formalism. A remarkable distinction between the thickness dependent effective masses extracted from the TB and the bulk values imply that the quantum confinement modifies the device performance. Strong transverse confinement leads to the effective Schottky barrier height increment. Owing to the adequate enhanced Schottky barriers at low drain voltages, a double barrier gate modulated potential well is formed along the channel. The double barrier profile creates a longitudinal quantum confinement and induces drain current oscillation at low temperatures. Significant factors that may affect the current oscillation are thoroughly investigated. Current oscillation is gradually smoothed out as the gate length shrinks down in ultra scaled structure. The results in this paper are paving a way to clarify the feasibility of this device in nanoscale regime.

Mobility- and temperature-dependent device model for amorphous In–Ga–Zn–O thin-film transistors

A device model for amorphous In–Ga–Zn–O thin-film transistors (a-IGZO TFTs) that explains temperature dependence is proposed. It incorporates a carrier-density dependent mobility and a density of subgap traps of a-IGZO. The model parameters were extracted from only one transfer curve of an a-IGZO TFT at a low drain voltage through a simple analytical model. Device simulation based on this model reproduced current- and mobility-gate voltage characteristics of the a-IGZO TFT well over a wide range of bias voltage and temperature (253–393K).

Tight-binding analysis of current oscillation in nanoscale In0.53Ga0.47As Schottky MOSFET

A comprehensive study of band structure effect on the quantum transport of nanoscale In0.53Ga0.47As Schottky MOSFET for the implementation of III–V MOSFET with low source/drain series resistance is presented. Rigorous treatment of the full band structure in ultra-thin body MOSFET is employed using sp3d5s* tight-binding approach. Strong transverse confinement increases the energy of subbands and, indeed, the effective Schottky barrier height. Due to enhanced Schottky barriers and at low drain voltages, a double barrier gate modulated potential well is created along the channel that results in source-to-drain confinement of states. As tunnelling is the main current component in this device, longitudinal confinement induces drain current oscillation at low temperatures. Important factors that may affect current oscillation are demonstrated. Current oscillation that alters the normal performance of the device is investigated in nanowire Schottky MOSFET, as well. Additional quantum confinement in nanowire Schottky MOSFET provides higher effective Schottky barrier height than the double gate structure. Accordingly, the drain current oscillation is more apparent in nanowire Schottky MOSFET than in the double gate device and is gradually smoothed out as the gate length shrinks down in ultra-scaled structure. Effect of diffusive scattering on the quantum transport of the device is investigated, too. What is prominent in our result is that the drain current oscillations degrade as the channel mobility is decreased. The results in this paper are paving a way to elucidate the feasibility of this device in the nanoscale regime.

Scaling of GaN HEMTs and Schottky Diodes for Submillimeter-Wave MMIC Applications

In this paper, we report state-of-the-art high frequency performance of GaN-based high electron mobility transistors (HEMTs) and Schottky diodes achieved through innovative device scaling technologies such as vertically scaled enhancement and depletion mode (E/D mode) AlN/GaN/AlGaN double-heterojunction HEMT epitaxial structures, a low-resistance <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$n^{+}$</tex></formula> -GaN/2DEG ohmic contact regrown by MBE, a manufacturable 20-nm symmetric and asymmetric self-aligned-gate process, and a lateral metal/2DEG Schottky contact. As a result of proportional scaling of intrinsic and parasitic delays, an ultrahigh <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$f_{T}$</tex></formula> exceeding 450 GHz (with a simultaneous <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$f_{\rm max}$</tex></formula> of 440 GHz) and a <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$f_{\rm max}$</tex></formula> close to 600 GHz (with a simultaneous <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$f_{T}$</tex></formula> of 310 GHz) are obtained in deeply scaled GaN HEMTs while maintaining superior Johnson figure of merit. Because of their extremely low on-resistance and high gain at low drain voltages, the devices exhibited excellent noise performance at low power. 501-stage direct-coupled field-effect transistor logic ring oscillator circuits are successfully fabricated with high yield and high uniformity, demonstrating the feasibility of GaN-based E/D-mode integrated circuits with <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${&gt;}{1000}$</tex> </formula> transistors. Furthermore, self-aligned GaN Schottky diodes with a lateral metal/2DEG Schottky contact and a 2DEG/ <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$n^{+}$</tex></formula> -GaN ohmic contact exhibited <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$RC$</tex></formula> -limited cutoff frequencies of up to 2.0 THz.

InGaAs/InP heterojunction-channel tunneling field-effect transistor for ultra-low operating and standby power application below supply voltage of 0.5 V

An In0.53Ga0.47As/InP heterojunction-channel tunneling field-effect transistor (TFET) with enhanced subthreshold swing (S) and on/off current ratio (Ion/Ioff) is studied. The proposed TFET achieves remarkable characteristics including S of 16.5 mV/dec, on-state current (Ion) of 421 μA/μm, Ion/Ioff of 1.2 × 1012 by design optimization in doping type of In0.53Ga0.47As channel at low gate (VGS) and drain voltages (VDS) of 0.5 V. Comparable performances are maintained at VDS below 0.5 V. Moreover, an extremely fast switching below 100 fs is accomplished by the device. It is confirmed that the proposed TFET has strong potentials for the ultra-low operating power and high-speed electron device.

Tight-binding study of quantum transport in nanoscale GaAs Schottky MOSFET

This paper explores the band structure effect to elucidate the feasibility of an ultra-scaled GaAs Schottky MOSFET (SBFET) in a nanoscale regime. We have employed a 20-band sp3d5 s* tight-binding (TB) approach to compute E — K dispersion. The considerable difference between the extracted effective masses from the TB approach and bulk values implies that quantum confinement affects the device performance. Beside high injection velocity, the ultra-scaled GaAs SBFET suffers from a low conduction band DOS in the Γ valley that results in serious degradation of the gate capacitance. Quantum confinement also results in an increment of the effective Schottky barrier height (SBH). Enhanced Schottky barriers form a double barrier potential well along the channel that leads to resonant tunneling and alters the normal operation of the SBFET. Major factors that may lead to resonant tunneling are investigated. Resonant tunneling occurs at low temperatures and low drain voltages, and gradually diminishes as the channel thickness and the gate length scale down. Accordingly, the GaAs (100) SBFET has poor ballistic performance in nanoscale regime.

극저온에서 나노스케일 무접합 p-채널 다중 게이트 FET의 전기적 특성

In this paper, the electrical properties of nanoscale junctionless p-channel MuGFET at cryogenic temperature have been analyzed experimentally. The experiment was performed using a cryogenic probe station which uses the liquid Helium. It has been observed that the drain current oscillation at low drain voltage and cryogenic temperature was more pronounced in junctionless transistor than in accumulation mode transistor. The reason for more marked oscillation is due to the smaller electrical cross section area of the inversion channel which is formed at the center of silicon film in junctionless transistor. It was also observed that the drain current and maximum transconductance were increased as the measurement temperature increased. This is resulted from the increase of hole mobility and the decrease of the threshold voltage as the measurement temperature increases. The drain current oscillation due to the quantum effects can be occurred up to the room temperature when the device size scales down to the nanometer level.

Performance assessment of nanoscale Schottky MOSFET as resonant tunnelling device: Non-equilibrium Green’s function formalism

A comprehensive study is performed on the electrical characteristics of Schottky barrier MOSFET (SBMOSFET) in nanoscale regime, by employing the non-equilibrium Green’s function (NEGF) approach. Quantum confinement results in the enhancement of effective Schottky barrier height (SBH). High enough Schottky barriers at the source/drain and the channel form a double barrier profile along the channel that results in the formation of resonance states. We have, for the first time, proposed a resonant tunnelling device based on SBMOSFET in which multiple resonance states are modulated by the gate voltage. Role of essential factors such as temperature, SBH, bias voltage and structural parameters on the feasibility of this device for silicon-based resonant tunnelling applications are extensively studied. Resonant tunnelling appears at low temperatures and low drain voltages and as a result negative differential resistance (NDR) is apparent in the transfer characteristic. Scaling down the gate length to 6 nm increases the peak-to-valley ratio (PVR) of the drain current. As the effective SBH reduces, the curvature of the double barrier profile is gradually diminished. Therefore, multiple resonant states are contributed to the current and consequently resonant tunnelling is smoothed out.

2-D Compact Model for Drain Current of Fully Depleted Nanoscale GeOI MOSFETs for Improved Analog Circuit Design

Compact models for MOS devices are extremely useful as they can be incorporated in circuit simulators with sufficient accuracy. We present for the first time a 2-D surface-potential-based compact model for the drain current of nanoscale germanium-on-insulator (GeOI) MOSFETs including the interface-trapped and fixed-oxide charge densities at both front- and back-gates. The proposed drain current model is accurate, computationally efficient, and suitable for circuit simulation in the nanometer regime because no iterative loop is used anywhere. The drain current model includes velocity saturation, channel length modulation, carrier mobility degradation, and also the drain-induced barrier lowering. The model shows excellent concordance with the reported experimental transfer characteristic curves for both the high and low drain voltages and also exhibits good agreement for derivatives of drain current when compared with our TCAD simulation data for GeOI devices with channel length of 30 nm over a wide range of gate and drain bias conditions. Furthermore, our studies reveal that GeOI devices outperform silicon-on-insulator (SOI) counterparts in terms of analog figures of merit, such as transconductance, voltage gain, transconductance generation factor, and cut-off frequency, except the output conductance.

Temperature Dependences of Transistor Characteristics of Single-Drain and Lightly-Doped-Drain Poly-Si TFTs

We have compared temperature dependences of transistor characteristics between single-drain (SD) and lightly-doped-drain (LDD) poly-Si thin-film transistors (TFTs). It is found that the temperature dependence of the off-leakage current for the LDD TFT is larger because the electric field at the drain junction is weaker. Moreover, the change of the temperature dependence from low drain voltage (V ds) to high V ds for the LDD TFT is smaller because the main mechanism of the off-leakage current is always phonon-assisted tunneling, whereas that for the SD TFT shifts from the phonon-assisted tunneling to the band-to-band tunneling.

Drain-conductance optimization in nanowire TFETs by means of a physics-based analytical model

In this work we propose a physics-based analytical model of nanowire tunnel FETs, which is meant to provide a fast tool for an optimized device design. The starting point of the model is the Landauer expression of the current for 1D physical systems, augmented with suitable expressions of the tunneling probability across the tunnel junctions and the whole channel. So doing, we account for the ambipolar effect, as well as for the tunnel-related leakage current, which becomes appreciable when small band-gap materials are used. The model is validated by comparison with numerical simulation results provided by the k·p technique. With this model we examine the problem of the non-linear output characteristics of tunnel FETs, and the related small drain conductance at low drain voltage, which prevents rail-to-rail logic switching, and design a nanowire TFET by an appropriate selection of the material, nanowire size and degeneracy levels in the source and drain regions.

True planar InAs/AlSb HEMTs with ion-implantation technique for low-power cryogenic applications

In this paper, we report the room-temperature and cryogenic properties of true planar 110nm InAs/AlSb HEMTs fabricated with Ar-ion isolation technology. Device isolation is generally improved and is in particular increased by four orders of magnitude at 6K compared to 300K. This results in improved drain current saturation, lower gate leakage current and 23% higher peak transconductance. The RF performance is significantly improved as well, with 47% higher fT (162GHz) and 72% higher fmax (155GHz) at the low drain voltage of 0.1V, compared to room temperature. The overall performance of the fabricated devices shows the suitability of ion implantation for the device isolation at cryogenic temperature. Furthermore, the excellent stability against oxidation and truly planar structure of these devices demonstrate great potential for highly integrated cryogenic millimeter-wave circuits in InAs/AlSb technology with ultra-low power consumption.