Low Drain Current Research Articles

Dual-gate AlGaN channel HEMTs: advancements in E-mode performance with N-shaped graded composite barriers

Abstract This work evaluates the performance of dual gate AlGaN channel HEMTs on SiC substrate. The study analyzes two HEMT structures that differ only in barrier design, one design consists of fixed composite barriers (FCB-HEMT) i.e. there is fixed Aluminum composition x = 0.48 in the first Al x Ga1−x N barrier and x = 0.42 in the second Al x Ga1−xN barrier while the other design comprises N-shaped graded composite barriers (NGCB-HEMT) i.e. the Aluminum content varies gradually from 0.4 to 0.48 in the first AlGaN barrier and from 0.34 to 0.42 in the second AlGaN barrier. The paper concentrates on energy band diagrams, electron concentration profile, electric field distribution, drain and transfer characteristics, and the effects of high temperature on drain characteristics and mobility of the NGCB-HEMT. It has been reported that at zero gate bias, the FCB-HEMT has a drain current density of 0.137 A mm−1 while it decreases to 0.0058 A mm−1 in the case of NGCB-HEMT, thus presenting a novel approach towards enhancement-mode AlGaN HEMTs. Hence, grading can be optimized in the composite barriers to achieve enhancement mode operation of AlGaN channel HEMTs. Furthermore, the study reveals that the critical electric field of FCB-HEMT is 6.9975 M V cm−1, while that of NGCB-HEMT is 5.3124 M V cm−1, demonstrating their usefulness in electronic devices that operate at high voltages and harsh temperatures. Moreover, at higher temperatures, the phenomenon of optical phonon scattering leads to decreased mobilities, which in turn causes low drain currents relative to the drain voltage.

Low-Thermal-Budget Ferroelectric Field-Effect Transistors Based on CuInP2S6 and InZnO.

In this paper, we demonstrate low-thermal-budget ferroelectric field-effect transistors (FeFETs) based on the two-dimensional ferroelectric CuInP2S6 (CIPS) and oxide semiconductor InZnO (IZO). The CIPS/IZO FeFETs exhibit nonvolatile memory windows of ∼1 V, low off-state drain currents, and high carrier mobilities. The ferroelectric CIPS layer serves a dual purpose by providing electrostatic doping in IZO and acting as a passivation layer for the IZO channel. We also investigate the CIPS/IZO FeFETs as artificial synaptic devices for neural networks. The CIPS/IZO synapse demonstrates a sizable dynamic ratio (125) and maintains stable multilevel states. Neural networks based on CIPS/IZO FeFETs achieve an accuracy rate of over 80% in recognizing MNIST handwritten digits. These ferroelectric transistors can be vertically stacked on silicon complementary metal-oxide semiconductor (CMOS) with a low thermal budget, offering broad applications in CMOS+X technologies and energy-efficient 3D neural networks.

Low-frequency noise characteristics of indium–gallium–zinc oxide ferroelectric thin-film transistors with metal–ferroelectric–metal–insulator–semiconductor structure

We investigate the low-frequency noise characteristics of indium–gallium–zinc oxide ferroelectric thin-film transistors (FeTFTs) with a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structure. MFMIS FeTFTs are fabricated with different metal-to-FE area ratios (AM/AF's). It is revealed that the noise generation mechanism differs depending on the operation region [low and high drain current (ID) regions] and AM/AF. Excess noise in the low ID region is observed in the MFMIS FeTFTs with AM/AF's of 4 and 6 due to carrier mobility fluctuations. In the high ID region, the carrier number fluctuation generates the 1/f noise of the devices regardless of the AM/AF.

Distinct Contact Scaling Effects in MoS2 Transistors Revealed with Asymmetrical Contact Measurements.

2D semiconducting materials have immense potential for future electronics due to their atomically thin nature, whichenables better scalability. While the channel scalability of 2D materials has been extensively studied, the current understanding of contact scaling in 2D devices is inconsistent andoversimplified. Here physically scaled contacts and asymmetrical contact measurements (ACMs) are combined to investigate the contact scaling behavior in 2D field-effect transistors. The ACMs directly compare electron injection at different contact lengths while using the exact same MoS2 channel, eliminating channel-to-channel variations.Theresults show that scaled source contacts can limit the drain current, whereas scaled drain contacts do not. Compared to devices with long contact lengths, devices with short contact lengths (scaled contacts) exhibit larger variations, 15% lower drain currents at high drain-source voltages, and a higher chance ofearly saturation and negative differential resistance. Quantum transport simulations reveal that the transfer length of Ni-MoS2 contacts can be as short as 5nm. Furthermore,it isclearly identified that the actual transfer length depends on the quality of the metal-2D interface. The ACMs demonstrated here will enable further understanding of contact scaling behavior at various interfaces.

Impact of doping concentration and recess depth to achieve enhancement mode operation in β-Ga2O3 MOSFET

High power switching applications necessitates the MOSFET to operate in Enhancement mode (normally OFF). Achieving enhancement mode operation in β-Ga2O3 MOSFET is challenging due to the difficulty in p-type doping. A TCAD simulation study is implemented to study the effect of the variation of doping concentration and recess gate to achieve enhancement mode operation. Subsequently, the device characteristics such as Id-Vd, Id-Vg and breakdown analysis are performed for β-Ga2O3 MOSFET with a channel thickness of 240 nm. On decreasing the doping concentration, the magnitude of threshold voltage reduces to 0V at a doping concentration of 1 × 1016 cm−3 causing enhancement mode operation but with significantly low drain current. However, this resulted in the increase in the device breakdown voltage. Adding Si3N4 passivation layer, further, enhanced the breakdown voltage. Subsequent study involved the impact of recessed gate to achieve enhancement mode operation. On increasing the recess depth, the magnitude of threshold voltage is reduced to 0V at a doping concentration of 8 × 1017 cm−3 with less impact on drain current. This also resulted in the increase in the device breakdown voltage. The obtained results will be instrumental for Ga2O3 community to develop and design enhancement mode β-Ga2O3 MOSFET for high power and high voltage applications.

인공 신경망 모델을 이용한 Work Function Variation (WFV), Random Dopant Fluctuation (RDF)가 유발하는 5㎚ 노드 FinFET의 전기적 특성 변화 예측

Work function variation (WFV), Random dopant fluctuation (RDF) 현상은 FinFET에서 발생하는 Process-induced variation 현상의 주요 원인이다. 본 연구에서는 5nm 노드 FinFET에서 WFV/RDF가 유도하는 전기적 소자 특성의 변동 예측을 위해 Artificial neural network (ANN) 모델을 사용한 발전된 방법을 제안한다. 본 논문에서의 ANN 모델은 4개의 input feature [i.e., Average grain size(AGS), Source/Drain doping density(S/D doping), Retrograde channel doping concentration(RCD doping), Retrograde channel doping peak point(RCD Peak)]를 사용해서 소자 성능을 나타내는 7개 output feature [i.e., off-state leakage current(ISUBoff/SUB), saturation drain current(ISUBdsat/SUB), linear drain current(ISUBdlin/SUB), low drain current(ISUBdlo/SUB), high drain current (ISUBdhi/SUB), saturation threshold voltage(VSUBtsat/SUB) and linear threshold voltage(VSUBtlin/SUB)]를 예측한다.

Specific Design Features of Charge Sensitive Amplifiers on Arsenide-Gallium Master Slice

For the production of integrated analog circuits with a small-scale integration, which are developed to operate at temperatures up to minus 200 ℃ and/or with absorbed dose of gamma radiation up to 5 Mrad, a gallium arsenide master slice has been created. The following types of active elements are used in this master slice: DpHEMT with gate dimensions 100 ηm/0,2 ηm and 10 ηm/0,2 ηm; p-n-p HBT, they were chosen for realization of most common analog circuits of operational amplifiers, comparators, voltage followers. Despite the small number of available DpHEMT with high transconductance for circuit synthesis and volt-ampere characteristics features of DpHEMT experimental samples, which exclude use of those transistors at low drain current, master slice give opportunity for developing charge-sensitive amplifiers (CSA) circuits with only one type of active elements – DpHEMT. At the same time, correct choice of the operating point of transistors provide development of low-noise, high-speed CSAs with better parameters than silicon CSAs for sensors with internal capacitance up to 100 pF. So, developed on GaAs master slice CSA with head DpHEMTs and ratio of the gate width to its length, equal to W/L = 2000 and W/L = 3000, characterized by current consumption ICC = 5,46 mA and ICC = 5,25 mA, rise time tR = 10,7 ns and tR = 9,6 ns, equivalent noise charge ENC = 3960 el, and ENC = 3700 el. with sensor capacitance of 50 pF, while the CSA with a head silicon p-channel junction field-effect transistor has W/L = 3870, ICC = 6,99 mA, tR = 27,7 ns, ENC = 5360 el. with the same sensor capacitance.

Design of JL-CFET (junctionless complementary field effect transistor)-based inverter for low power applications

Junctionless complementary field effect transistor (JL-CFET) is an emerging device that needs a small layout area and low fabrication cost. However, in order for the JL-CFET to be adopted for low power applications, two main constraints need to be overcome: (a) a high work function of metal gate and (b) a low drain current. In this work, an optimal device design is proposed to overcome those problems, by analyzing various performance metrics, such as on-state drive current, subthreshold swing, drain induced barrier lowering, propagation delay time, and ring oscillator’s oscillation frequency, which are extracted from various structures of JL-CFET. In addition, the negative capacitance effect in JL-CFET is examined to address the limit from device structures.

Impact of Contact Doping on Electrical Characteristics in WSe2 FET

Since layered semiconductor tungsten diselenide (WSe2) has no dangling bond and a relatively large band gap, it is expected as a channel material for an application of field effect transistor (FET)[1]. On the other hand, high energy process destroys the crystal structure of the layered semiconductor. In this context, carrier doping by the low energy process is important for improving the electrical characteristics. This study reports that CYTOP (9 wt%) was applied as a doping material on the WSe2 FET for p-type operation by spin coating and the impact of contact doping on the electrical characteristics was investigated. A SiO2 gate dielectric was formed on a heavily-doped p-Si substrate (p+-Si) using thermal oxidation for back-gate structure. Next, a source / drain of Au (40 nm) / Ti (10 nm) was prepared by using photolithography and lift-off. Using a PDMS stamp and a micromanipulator, WSe2, which was mechanically peeled off using Scotch tape, was transferred between the source and drain to fabricate a back-gate WSe2 FET. After measuring the electrical characteristics without CYTOP, CYTOP was applied on the WSe2 FET surface using a spin coating. Then, the electrical characteristics with CYTOP were measured again. In this study, the annealing was performed for 30min at 200 ° C and 250 ° C. Id-Vg characteristics as a function of annealing temperature of the fabricated back gate WSe2 FET are shown in Fig. 1. From the Fig. 1, it can be confirmed that WSe2 FET shows p-type operation. Moreover, it can be confirmed that the drain current increases by applying the CYTOP, while the low drain current was observed without CYTOP. It was found that the drain current was increased with increasing the annealing temperature.[Acknowledgments]The authors would like to thank Professor Y. Kawano, Professor T. Hoshii, Professor I. Muneta, Professor K. Kakushima, Professor K. Tsutsui, and Professor H. Wakabayashi of Tokyo Institute of Technology for their continuous support in the experiments. This study was supported by JST CREST (Grant No. JPMJCR16F4) and a JSPS Grant-in-Aid for Scientific Research (C) (Grant No. 20K04616).[References][1] In-Tak Cho et al., Applied Physics Letters 106, 023504 (2015). Figure 1

InP HEMTs for Sub-mW Cryogenic Low-Noise Amplifiers

This paper reports on a 100-nm gate length InP high-electron-mobility transistor (HEMT) technology for cryogenic low-noise amplifiers (LNAs) with ultra-low power dissipation of $112~\mu \text{W}$ . This result was obtained by using 100-nm gate length InP HEMTs with improved transconductance at low drain current through a scaled-down gate-channel distance while maintaining a low gate leakage current with the use of an InP etch stop layer and Pt gate metal. The noise performance of InP HEMTs was demonstrated in a 4–8 GHz (C–band) three-stage hybrid LNA at the ambient temperature of 5 K. At a dc power dissipation of $300~\mu \text{W}$ , the average noise temperature was 2.8 K with 27 dB gain. At a dc power dissipation of $112~\mu \text{W}$ , the LNA exhibited an average noise temperature of 4.1 K with a gain of 20 dB. The presented results demonstrate the large potential of InP HEMT technology for sub-mW cryogenic LNA design.

Evaluation of Minority Carrier Generation Lifetime for Oxide Semiconductors

In this study, the transfer characteristics of InGaZnO (IGZO) and InSnZnO (ISZO) thin-film transistors are compared using the minority carrier generation lifetime method. Capacitance-voltage and capacitance-time characteristics of IGZO- and ISZO-based capacitors with a p+-Si/SiO2/IGZO or ISZO structure were evaluated at a 100 kHz frequency. Although the intrinsic carrier concentrations of IGZO and ISZO films are on the order of ~10−7 cm−3, which is conjectured to result in a very low off-state drain current (ID,OFF), even as small as zero, a magnitude of 10−12 – 10−11 A for ID,OFF was measured in this study. We propose that this is due to the minority carriers, which are thermally generated from the channel defects. Furthermore, ISZO films exhibited faster transient capacitance characteristics compared to the IGZO films, which is associated with the amount of defect sites in the channel substrate. Thus, the lower transient time for the ISZO films is attributed to a larger number of oxygen vacancies in the channel layer than in IGZO films.

Effects of p-GaN gate structures and fabrication process on performances of normally-off AlGaN/GaN high electron mobility transistors

Performances of AlGaN/GaN high electron mobility transistors (HEMTs) with various p-GaN gates structures were investigated. With the HEMT wafer surmounted by a p-GaN layer, the gates were formed utilizing inductively coupled plasma reactive ion etching. The etching rate ratio for GaN to AlGaN was obtained to be 50 employing O2 with added Cl2 and Ar gases. Three types of HEMTs with etched regions of p-GaN removed, AlGaN etched slightly, and p-GaN remained were fabricated. All HEMTs showed the same threshold voltage of 1.2 V. High drain currents were obtained for HEMTs of p-GaN removed and AlGaN etched slightly, while the p-GaN remained showed low drain current. On-resistances of p-GaN removed and AlGaN etched slightly HEMTs were 7.3 and 8.6 Ω mm, and electron mobilities were 1600 and 1100 cm2/(V·s). The higher on-resistance of the HEMT with AlGaN etched slightly is ascribed to the deteriorated electron mobility.

Enhancement of Johnson figure of merit in III‐V HEMT combined with discrete field plate and AlGaN blocking layer

The performance of AlGaN/GaN HEMT is enhanced by using discrete field plate (DFP) and AlGaN blocking layer. The AlGaN blocking layer provides an excellent confinement of electrons toward the GaN channel, resulting very low subthreshold drain current of 10−8 A/mm. It reveals very high off state breakdown voltage (BV) of 342 V for 250 nm gate technology HEMT. The breakdown voltage achieved for the proposed HEMT is 23% higher when compared to the breakdown voltage of conventional field plate HEMT device. In addition, the DFP reduces the gate capacitance (CG) from 12.04 × 10−13 to 10.48 × 10−13 F/mm. Furthermore, the drain current and transconductance (gm) reported for the proposed HEMT device are 0.82 A/mm and 314 mS/mm, respectively. Besides, the cut-off frequency (fT) exhibited for the proposed HEMT is 28 GHz. Moreover, the proposed HEMT records the highest Johnson figure of merit (JFOM) of 9.57 THz-V for 250 nm gate technology without incorporating T-gate.

An Analytical Model for the Effective Drive Current in CMOS Circuits

Inverter delay is often evaluated as CV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> , where C is the load capacitance, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> is the supply voltage, and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> is the effective drive current derived by approximating the inverter switching trajectory with a linear model. The I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> model utilizes high and low drain currents conventionally measured in wafer acceptance tests and does not require extraction of any parameters. Ease of use combined with reasonable accuracy (~15%) is the main reason for wide application of CV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> delay metrics. However, CV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> expression produces large errors when applied to another two important basic circuits: nand and nor. This is because nand and nor circuits contain transistor series connections not accounted for in the inverter model. In this paper, an analytical solution for the transistor series connection influence on the discharge/charge operation in nand/nor circuits is provided. The model for nand/nor effective drive current (denoted as Istack) developed in this paper maintains simplicity of the original I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> expression. It requires only one additional measurement of the linear current. Model accuracy was assessed by comparing to extensive SPICE delay simulations of nand and nor circuits designed using state-of-the-art MOS technologies. Comparison results show that CV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">stack</sub> equation provides ~15% accuracy for nand/nor circuits in line with CV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> accuracy for inverter. In an era of emphasis on low-power design, the developed model presents convenient means of exploring design space when optimizing circuit supply voltage for low-power operation.

High Performance Al0.10Ga0.90N Channel HEMTs

This letter reports the large maximum drain current AlGaN channel high-electron-mobility transistors (HEMTs) of 849 mA/mm with graded buffers and constant channel layer. The large drain current and the transconductance benefit from the high electronic mobility of 807 cm2/ $\mathrm {V}\cdot \mathrm {s}$ and high saturated velocity. Furthermore, the device also shows a low off-state drain current of ~1 nA/mm and an ultrahigh ${I} _{ \mathrm{\scriptscriptstyle ON}}/{I} _{ \mathrm{\scriptscriptstyle OFF}}$ up to ~109. To the best of the authors’ knowledge, the electronic mobility, the maximum drain current, and ${I} _{ \mathrm{\scriptscriptstyle ON}}/{I} _{ \mathrm{\scriptscriptstyle OFF}}$ ratio all are the largest reported results ever achieved on the AlGaN channel HEMTs. These results not only drastically reduce the performance gaps between the AlGaN channel HEMT and the GaN channel HEMT in the maximum drain current, the maximum transconductance, and the electronic mobility, but also demonstrate better performances in the gate leakage current, the off-state drain current, ${I} _{ \mathrm{\scriptscriptstyle ON}}/{I} _{ \mathrm{\scriptscriptstyle OFF}}$ ratio, and the breakdown voltage.

Influence of gate recess on the electronic characteristics of β-Ga2O3 MOSFETs

Gallium oxide (Ga2O3) metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated with gate recess depths of 110 nm and 220 nm, respectively. The gate recess was formed by dry plasma etching with Cr metal as the mask. The fabricated devices with a 25-nm HfO2 gate dielectric both showed a low off-state drain current of about 1.8 × 10−10 A/mm. The effects of recess depth on the electronic characteristics of Ga2O3 MOSFETs were investigated. Upon increasing the recess depth from 110 nm to 220 nm, the saturated drain current decreased from 20.7 mA/mm to 2.6 mA/mm, while the threshold voltage moved increased to +3 V. Moreover, the breakdown voltage increased from 122 V to 190 V. This is mainly because the inverted-trapezoidal gate played the role of a gate-field plate, which suppressed the peak electric field close to the gate.

Silicon tunnel FET with average subthreshold slope of 55 mV/dec at low drain currents

In this paper we present a silicon tunnel FET based on line-tunneling to achieve better subthreshold performance. The fabricated device shows an on-current of Ion = 2.55 × 10−7 A/µm at Vds = Von = Vgs − Voff = −0.5 V for an Ioff = 1 nA/µm and an average SS of 55 mV/dec over two orders of magnitude of Id. Furthermore, the analog figures of merit have been calculated and show that the transconductance efficiency gm/Id beats the MOSFET performance at low currents.

DC and RF Characteristics of Enhancement-Mode Al2O3/AlGaN/GaN MIS-HEMTs Fabricated by Shallow Recess Combined with Fluorine-Treatment and Deep Recess

Enhancement-mode (E-mode) Al2O3/AlGaN/GaN MISHEMTs were fabricated by shallow recess combined with CF4 plasma treatment (SR/F) and deep recess (DR) to compare the effect of each process technique on the device performance. To prevent the device performance degradation induced by plasma damage during gate recess, the digital etch technique was employed. The fabricated E-mode devices have positively shifted threshold voltage, and exhibit lower transconductance (gm) and saturation drain current than depletion-mode devices. Due to the CF4 plasma damage during F-treatment, SR/F shows a sharp drop of gm curve and low saturation drain current. In contrast, DR presents broad gm and high saturation drain current. It is also revealed that the digital etch for gate recess exhibits an isotropic etch profile, consequently increasing the on-resistance. There is no remarkable difference between SR/F and DR in fT and fmax, but DR has a better linearity over SR/F owing to the absence of plasma damage during F-treatment. This results reveal that the DR using digital etch is promising technique to obtain the high performance E-mode MISHEMTs compared to the F-treatment.

Effects of various bias and temperature stresses on low-frequency noise properties of amorphous InGaZnO thin-film transistors

The authors investigate the low-frequency noise (LFN) properties of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) under various bias and temperature stress conditions. After application of a gate-to-source bias (VGS) stress, the LFN properties hardly change. However, the LFN increases (especially, at low drain currents) after application of simultaneous VGS and drain-to-source bias (VDS) stresses. The LFNs measured before and after the stresses are well-fitted using the correlated number fluctuation-mobility fluctuation (Δn-Δμ) model, and the extracted values of the border trap density (NT) and the Coulomb scattering coefficient (αS) increase from 1018 eV−1 cm−3 and 105 V s/C to 1.53 × 1019 eV−1 cm−3 and 106 V s/C, respectively, after application of simultaneous gate- and drain-bias stresses (VGS = VDS = 20 V) for 1000 s at room temperature. This phenomenon is mainly attributed to the high electric-field-induced electronic trap generation inside the a-IGZO active layer. The increase in temperature during application of the simultaneous gate- and drain-bias stress accelerates the increase of LFN after the stress. The values of NT and αS are increased to 9.53 × 1019 eV−1 cm−3 and 8 × 106 V s/C, respectively, after the application of simultaneous gate- and drain-bias stresses for 1000 s at 80 °C, which are much higher than those extracted after the application of simultaneous gate- and drain-bias stresses at room temperature. This result shows that a high electric field combined with a high temperature significantly increases the density of electronic trap states which degrades the LFN properties in a-IGZO TFTs.

Double-Gate Modulated Corbino TFTs

Short-channel Corbino thin-film transistors (TFTs) exhibit infinite output resistance beyond pinchoff when the outer-ring electrode is biased as the drain but suffer from low drain currents. It is shown here that the employment of a thin (<25 nm) amorphous oxide semiconductor and a double-gate (DG) structure (with a top-gate electrically tied to a bottom-gate) increases the drain currents of the Corbino TFTs biased in the outer-drain condition by over two times through bulk-accumulation (BA), without compromising their infinite output resistance beyond pinchoff or bias, temperate, and light stability. By experiment and through 3-D TCAD simulations, evidence of BA under DG modulation and the origin of the infinite output resistance beyond pinchoff in Corbino TFTs are also revealed in this letter.