Effects of various bias and temperature stresses on low-frequency noise properties of amorphous InGaZnO thin-film transistors

Abstract

The authors investigate the low-frequency noise (LFN) properties of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) under various bias and temperature stress conditions. After application of a gate-to-source bias (VGS) stress, the LFN properties hardly change. However, the LFN increases (especially, at low drain currents) after application of simultaneous VGS and drain-to-source bias (VDS) stresses. The LFNs measured before and after the stresses are well-fitted using the correlated number fluctuation-mobility fluctuation (Δn-Δμ) model, and the extracted values of the border trap density (NT) and the Coulomb scattering coefficient (αS) increase from 1018 eV−1 cm−3 and 105 V s/C to 1.53 × 1019 eV−1 cm−3 and 106 V s/C, respectively, after application of simultaneous gate- and drain-bias stresses (VGS = VDS = 20 V) for 1000 s at room temperature. This phenomenon is mainly attributed to the high electric-field-induced electronic trap generation inside the a-IGZO active layer. The increase in temperature during application of the simultaneous gate- and drain-bias stress accelerates the increase of LFN after the stress. The values of NT and αS are increased to 9.53 × 1019 eV−1 cm−3 and 8 × 106 V s/C, respectively, after the application of simultaneous gate- and drain-bias stresses for 1000 s at 80 °C, which are much higher than those extracted after the application of simultaneous gate- and drain-bias stresses at room temperature. This result shows that a high electric field combined with a high temperature significantly increases the density of electronic trap states which degrades the LFN properties in a-IGZO TFTs.