A study on the degradation mechanism of InGaZnO thin-film transistors under simultaneous gate and drain bias stresses based on the electronic trap characterization

Abstract

We discuss the device degradation mechanism of amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) under simultaneous gate and drain bias stresses based on the electronic trap characterization results. The transfer curve exhibits an apparent negative shift as the stress time increases, and a formation of hump is observed in the transfer curve after stresses. A notable increase of the frequency dispersion is observed after stresses in both gate-to-drain capacitance–voltage (CGD–VG) and gate-to-source capacitance–voltage (CGS–VG) curves, which implies that the subgap states are generated by simultaneous gate and drain bias stresses, and the damaged location is not limited to the drain side of TFTs. The larger frequency dispersion is observed in CGD–VG curves after stresses in a wider channel device, which implies that the heat is an important factor in the generation of the subgap states under simultaneous gate and drain bias stresses in a-IGZO TFTs. Based on the electronic trap characterization results, we conclude that the impact ionization near the drain side of the device is not a dominant mechanism causing the generation of subgap states and device degradation in a-IGZO TFTs under simultaneous gate and drain bias stresses. The generation of oxygen vacancy-related donor-like traps near the conduction band edge is considered as a possible mechanism causing the device degradation under simultaneous gate and drain bias stresses in a-IGZO TFTs.