Device Degradation Under High Gate and Drain Bias Stress in IGZO Transistors

Abstract

The device degradation in InGaZnO thin film transistor has been investigated experimentally under high gate and drain bias stress. The transfer curve was positively shifted and the threshold voltage was increased after high gate and drain bias stress. This may be attributed to the trapped electron charges resulted from the injection of channel hot electrons. The threshold voltage shift is more significant after high gate and drain bias stress than after high gate bias stress. The device degradation can be predicted by the monitoring of the gate current. The device degradation is the most significant under high gate drain bias stress and light illumination at elevated temperature.