Threshold-voltage instability of polymer thin-film transistor under gate-bias and drain-bias stresses

Abstract

Polymer thin-film transistors (PTFTs) based on MEH-PPV semiconductor are fabricated by spin-coating process and characterized. Gate-bias and drain-bias stress effects at room temperature are observed in the devices. The saturation current decreases and the threshold voltage shifts toward negative direction upon the gate-bias stress. However, the saturation current increases and the threshold voltage shifts toward positive direction upon the drain-bias stress. For variable bias stress conditions, carrier mobility is almost unchanged. The results suggest that the origin of threshold-voltage shift upon negative gate-bias stress is predominantly associated with holes trapped within the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate dielectric or at the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si interface due to hot-carrier emission under high gate-bias stress, while time-dependent charge trapping into the deep trap states in the channel region is responsible for the drain-bias stress effect in the PTFTs.