Modelling the threshold-voltage shift of polymer thin-film transistors under constant and variable gate-bias stresses

Abstract

Polymer thin-film transistors based on poly(2-methoxy-5-(2′-ethyl-hexyloxy)-1,4-phenylene vinylene) semiconductors are fabricated by a spin-coating process and characterized. The effects of gate-bias stress on the devices at room temperature are studied. Upon the gate-bias stress, the saturation current decreases; threshold voltage shifts toward the negative direction, but carrier mobility remains essentially constant. Quasi-static capacitance–voltage analysis on a metal-oxide-semiconductor capacitor structure is used to clarify the physical mechanism of the threshold-voltage shift. A model for the threshold-voltage shift under constant and variable gate-bias stresses is proposed and shows good agreement with experimental data.