Low Base Resistance Research Articles

Experimental investigation of bearing mechanism of closed- and open-ended piles supported by thin bearing layer using X-ray micro CT

In order to clarify the bearing mechanism of closed-ended and open-ended piles supported by a thin bearing layer, pile-loading tests are conducted on model grounds with different bearing layer thicknesses, and the soil deformation characteristics around the pile tips are observed by X-ray micro CT. In the case of open-ended piles supported by a thin bearing layer, the soil in the pile greatly displaces following the downward displacement of the soil located more deeply than the pile tip, and the soil density in the pile becomes lower than when the bearing layer thickness is sufficiently large. These characteristics probably cause lower inner friction and lower base resistance, resulting in a lower bearing capacity. When the bearing layer thickness is more than three times the pile diameter, the bearing capacity is much higher than when the bearing layer thickness is the same as the pile diameter. In addition, soil deformation which occurs is almost entirely in the bearing layer, and the changes in bearing capacity are hardly affected by the soft layer below the bearing layer. The experimental findings obtained in the present study support the idea that the criterion for the bearing layer thickness, where the influence of a thin bearing layer on the bearing capacity can be ignored, is three times the pile diameter, regardless of whether the pile tip is open or closed.

Gas-sensing properties of In-=SUB=-2-=/SUB=-O-=SUB=-3-=/SUB=--Ga-=SUB=-2-=/SUB=-O-=SUB=-3-=/SUB=- alloy films

The effect of the gaseous medium composition on the electrically conductive properties of In2O3-Ga2O3 films obtained by halide vapor phase epitaxy has been studied. In the temperature range of 100-550oC, the In2O3-Ga2O3 films exhibit high sensitivity to H2, NH3 and possess hyphen performance and low base resistance. A qualitative mechanism for the sensitivity of In2O3-Ga2O3 films to gases is proposed. Keywords: In2O3-Ga2O3, halide vapor-phase epitaxy, gas sensitivity.

Visible light boosting hydrophobic ZnO/(Sr0.6Bi0.305)2Bi2O7 chemiresistor toward ambient trimethylamine

Though UV illumination has been widely adopted to activate the room temperature response of metal oxide based chemiresistors, photoexcited abundant carriers (low base resistance) induced low response, and UV induced hydrophilicity caused degradation or even poisoning in ambient humid air atmosphere, pose a challenge for real applications. Herein, 15 mol% (optimized ratio) ZnO nanoparticles have been coupled into hydrophobic (Sr0.6Bi0.305)2Bi2O7 (SBO) matrix, hydrophobic ZnO/SBO chemiresistor has been proposed. Visible 455 nm light could not only trigger the gas/oxide interfacial charge exchange, but also substantially reduce the carrier concentration of chemiresistor in comparison with UV 365 nm light, and therefore noticeably boosts trimethylamine (TMA) response at room temperature, including an enlarged sensitivity, extremely low limit of detection (LoD) (10 ppb), good selectivity, reproducibility and long-term stability. More importantly, present hydrophobic ZnO/SBO chemiresistor could be operated under high relative humidity (RH 90%) with a slight decline (17%) of response with respect to dry air background, opening an opportunity for the practical applications of oxide chemiresistors in ambient humid atmosphere.

A Comparative Study of InGaP/GaAs Collector-Up HBTs for High-Reliability Small-Scale PA Applications

In this paper, the characteristics of InGaP/GaAs collector-up (C-up) pnp and npn heterojunction bipolar transistors (HBTs) with the graded InGaAs base and the nonuniform doped collector are demonstrated, and the performances as well as the reliability of the novel HBTs have been compared with the conventional InGaP/GaAs HBTs with various collector structures and thermal schemes. Compared to conventional HBTs, the studied C-up HBTs exhibited better current-driving capability, higher RF efficiency, and improved long-term reliability. Note that the pnp device displayed greater thermal stability enhancements, which are distinct and reproducible, than the npn device. The favorable data of the pnp C-up HBT could be attributed to higher electron mobility, resulting in low base resistance and higher emitter resistance improving the thermal stability. The comparison results, based on pragmatic observations from the C-up HBTs without relatively large heat-dissipation configurations, should be very useful for the reliable and the cost-effective design as small-scale power amplifiers in the wideband CDMA system.

Investigation of Disilane-Based SiGe-HBT Layers for Low External Base Resistances

In the past decade there has been increased interest in utilizing SiGe-heterojunction bipolar transistors (SiGe-HBT) and in particular SiGe-BiCMOS technologies for applications in the mm-and sub-mm-wave range. High data rate communication systems and optical networks for >100Gb/s, industrial and automotive sensors at 120 GHz for velocity and position control as well as imaging systems at >160 GHz for medical and security systems are some examples for these fields of application. Key elements for the continuous improvement of the high frequency performance of SiGe-HBTs are the scaling of vertical and lateral dimensions as well as design optimization to achieve reduced parasitics. In particular the maximum oscillation frequency fmax could be increased in the last years above 0.5 THz. Beside a sufficient high cut-off frequency fT, a reduced base-collector capacitance CBC and low base resistance RB are beneficial for the fmax performance of a SiGe-HBT. In this work we investigate the behavior of the external base resistance RBext for two different epitaxial processes used in SiGe-HBTs with a silane- (SiH4) and disilane-based (Si2H6) precursor. The SiGe-layers were treated by various rapid thermal annealing (RTA). We processed different wafers with an oxide stack usually used in a standard SiGe-BiCMOS process. After the release of certain silicon regions by reactive-ion-etching the epitaxial layers were deposited. First a selective epitaxial silicon buffer was grown within oxide-free windows followed by non-selective growth of a silicon layer, the in-situ boron doped SiGe base layer and an on top silicon cap layer. For the disilane-based process the SiGe layer grows in an amorphous phase whereas for the silane-based process a poly-crystalline film is formed. The growth of the whole Si-SiGe-Si stack was adapted for disilane process in order to reach the same layer thicknesses for both variants inside oxide free windows (single-crystalline regions) as for the original silane-based process. Sheet resistance (Rs) measurements were performed on 49 points across a wafer on the poly crystalline SiGe layer on an oxide. Figure 1 shows the Rs of silane-based (#1) and disilane-based (#3) SiGe-layer after a rapid thermal annealing at 1010°C for 12s. We observe a decrease of Rs by 60% in comparison to the silane-based SiGe-layer. Even for a reduced annealing temperature of 950°C (#2) the Rs dropped down around 30% in comparison to the silan-based variant. Moreover the standard deviation of the sheet resistance in the poly-crystalline regions across the wafer becomes significantly smaller and decreased by a factor of six down to approximately 50 Ohm/square for the disilane-based SiGe stack. Secondary-ion-mass-spectroscopy (SIMS) measurements were used to characterize the boron doping and SiGe-profile inside the crystalline and poly-crystalline regions of the wafers. In the poly crystalline region the germanium and boron concentration of the disilane-based process corresponds to the distribution of the single crystalline region. However we obtain a difference in the doping distribution after epitaxy (Fig. 2a) in comparison to the silane-based process. This difference becomes more significant after the RTA and we observe a quite homogeneous distribution of Ge and boron for the silane-based SiGe-stack whereas a steeper doping is within poly-crystalline layers for the disilane-based process (Figure 2b). We address this disparity in the Ge and boron distribution to differences in the diffusion behavior for the disilane-based layer stack due to i) the deposition as an amorphous Si/SiGe/Si layer and ii) the grain size of the poly-crystals after the final RTA. For our operation point the loading effect during the disilane-based epi-process leads to a 40% increased boron dose in the external base region compared to the silane-based process and without increasing the B doping inside the single crystalline region. This is beneficial for the behavior of RBext. Finally we applied both variants in a standard SiGe-BiCMOS flow. The overall performance of the SiGe-HBT depends of course on several other aspects like base-emitter and base-collector capacitances and the influence of changing one parasitic component has to be carefully evaluated. Nevertheless the external base resistance as well as the contact resistance dropped by 55% and 45%, respectively, for the disilane-based process and show the benefits for the use of this type of epitaxial layer depositions in advanced SiGe-HBTs. Figure 1

A Class-E Tuned W-Band SiGe Power Amplifier With 40.4% Power-Added Efficiency at 93 GHz

A W-band power amplifier with Class-E tuning in a 0.13 $\mu{\rm m}$ SiGe BiCMOS technology is presented. Voltage swing beyond $BV_{\rm CBO}$ is enabled by the cascode topology, low upper base resistance, and minimally overlapping current-voltage waveforms. At 93 GHz with 4.0 V bias, the peak power-added efficiency and saturated output power are measured to be 40.4% and 17.7 dBm, respectively. With the bias increased to 5.2 V, the peak power-added efficiency and saturated output power at 93 GHz are measured to be 37.6% and 19.3 dBm, respectively.

SiGe HBT CML Ring Oscillator With 2.3-ps Gate Delay at Cryogenic Temperatures

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> We present a measured current-mode logic ring oscillator gate delay of 2.3 ps, a record for digital circuits in silicon-based technologies. This result was achieved in a silicon–germanium (SiGe) heterojunction bipolar transistor (HBT) technology operating at 25 K. In addition to higher cutoff frequency and lower collector-base capacitance, lower base resistance is also responsible for the improved switching speed at cryogenic temperatures. The self-heating characteristics of these SiGe HBT circuits are also investigated across temperatures. </para>

Self-aligned Process for SiC Power Devices

AbstractSilicon carbide is a semiconductor with desirable material properties, such as a wide bandgap and high thermal conductivity. It is an excellent material for constructing power switching devices operating in harsh environments where conventional semiconductors cannot adequately perform. One example of such a power device is a bipolar junction transistor (BJT). While the potential of the SiC BJT is recognized, appropriate techniques for producing devices is lacking due to its difficulty.For example, in order to achieve a high voltage 4H-SiC BJT switch with nanosecond switching time, the device must have a low base resistance. The simulation results indicate that for an emitter width of 2.0 μm and a base width of 1.2 μm the distance between the two should be 0.4 μm or less to meet the requirement for base resistance. To produce the above-described geometries and spacing, it is desirable to construct the device in a self-aligned manner. Self-alignment in this context means that the relative spacing of features of the device, such as contacts, is automatically controlled by the processing sequence and process parameters, rather than by the careful alignment prior to exposure of a photo sensitive layer. For this purpose, we developed a novel self-aligned process for SiC BJT devices, that enables the fabrication of the design with high yield, as standard silicon self-aligned technique are not applicable.The newly developed process starts with the deposition of the emitter contact metal, which provides the metal mask for the etching of the emitter ridges. Next, the wafer is planarized with photoresist and etched, so that only the emitter contacts are exposed. Electroless plating is then used to enlarge the contacts, and after removal of the resist, the plating provides an overhang, suitable for lift-off of the base contact metal. After the base contact metal deposition, the structure is planarized and etched, this time with a silicon dioxide layer, again exposing the plated emitter contacts and the lift-off step is the wet etching of the plated metal. The emitters are then all connected with a blanket wiring level, which also forms the base contact pad. This process is simpler and more robust than the process we developed to date. The main difference is the inclusion of a sacrificial lift-off overhang, created by electroless plating. It enables a well controlled overhang independent of steepness of the SiC ridge profile and the height of the emitter mesa. We successfully fabricated the overhang structure on 4H-SiC substrates.In conclusion, we report the demonstration of a new self-aligned process, which provides a self-aligned emitter contact, a self-aligned base contact and eliminates the need for via holes smaller than the emitter stripe widths. We consider this new process a major improvement over existing processes to fabricate SiC BJT devices.

Strained-Silicon Heterojunction Bipolar Transistor

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Experimental and modeling results are reported for high-performance strained-silicon heterojunction bipolar transistors (HBTs), comprising a tensile strained-Si emitter and a compressively strained <formula formulatype="inline"><tex Notation="TeX">$\hbox{Si}_{0.7}\hbox{Ge}_{0.3}$</tex></formula> base on top of a relaxed <formula formulatype="inline"><tex Notation="TeX">$\hbox{Si}_{0.85}\hbox{Ge}_{0.15}$</tex></formula> collector. By using a <formula formulatype="inline"><tex Notation="TeX">$\hbox{Si}_{0.85}\hbox{Ge}_{0.15}$</tex></formula> virtual substrate strain platform, it is possible to utilize a greater difference in energy band gaps between the base and the emitter without strain relaxation of the base layer. This leads to much higher gain, which can be traded off against lower base resistance. There is an improvement in the current gain <formula formulatype="inline"><tex Notation="TeX">$\beta$</tex> </formula> of 27<formula formulatype="inline"><tex Notation="TeX">$\times$</tex></formula> over a conventional silicon bipolar transistor and 11<formula formulatype="inline"><tex Notation="TeX">$\times$</tex></formula> over a conventional SiGe HBT, which were processed as reference devices. The gain improvement is largely attributed to the difference in energy band gap between the emitter and the base, but the conduction band offset between the base and the collector is also important for the collector current level. </para>

Investigation of Thermal Stability in Multifinger GaInP/GaAs Collector-Up Tunneling–Collector HBTs With Subtransistor Via-Hole Structure

In this paper, thermal stability in the multifinger GaInP/GaAs collector-up tunneling-collector heterojunction bipolar transistors (C-up TC-HBTs) has been investigated. Two unique structures in these C-up TC-HBTs are provided for thermal management for a stable operation. One is the base layer that is incorporated with highly resistive regions, which serves as a ballast resistor, due to the boron-ion implantation. The other is the backside via-hole structure constructed underneath the transistors called "the subtransistor via-hole structure", leading to a superior thermal conduction. In this paper, as a result, it was revealed that the effect of the via hole on the thermal stability depends on the effect of the base resistance on the thermal stability. The thermal stability in the C-up TC-HBTs, with a relatively lower base resistance due to the boron-ion implantation of 1times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> , is attributed to the decrease in the thermal resistance due to the via hole, while that in the C-up TC-HBTs, with a boron-ion implantation of 2times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> , is dominated by a relatively large base resistance. Moreover, with a reduction in the finger space in the four-finger C-up TC-HBTs with a low base resistance, the range of a thermally stable operation is found to become narrower. This can be explained by the dependence of the thermal resistance on the finger space in the four-finger C-up TC-HBTs. These results are useful for the device design, so as to obtain the thermal stability in the C-up TC-HBTs with a subtransistor via-hole structure, for application in the small and high-power amplifiers

Noise in SiGe HBT RF Technology: Physics, Modeling, and Circuit Implications

This paper presents an overview of the physics, modeling, and circuit implications of RF broad-band noise, low-frequency noise, and oscillator phase noise in SiGe heterojunction bipolar transistor (HBT) RF technology. The ability to simultaneously achieve high cutoff frequency (f/sub T/), low base resistance (r/sub b/), and high current gain (/spl beta/) using Si processing underlies the low levels of low-frequency 1/f noise, RF noise, and phase noise of SiGe HBTs. We first examine the RF noise sources in SiGe HBTs and the RF noise parameters as a function of SiGe profile design, transistor biasing, sizing, and operating frequency, and then show a low-noise amplifier design example to bridge the gap between device and circuit level understandings. We then examine the low-frequency noise in SiGe HBTs and develop a methodology to determine the highest tolerable low-frequency 1/f noise for a given RF application. The upconversion of 1/f noise, base resistance thermal noise, and shot noises to phase noise is examined using circuit simulations, which show that the phase noise corner frequency in SiGe HBT oscillators is typically much smaller than the 1/f corner frequency measured under dc biasing. The implications of SiGe profile design, transistor sizing, biasing, and technology scaling are examined for all three types of noises.

Base resistance scaling for SiGeC HBTs with a fully nickel-silicided extrinsic base

A novel SiGeC HBT process with a quasi-self-aligned emitter-base architecture and a fully nickel-silicided extrinsic base region has been developed. A very low total base resistance R/sub B/ was achieved along with simultaneous NiSi formation on the polycrystalline emitter and collector regions. Uniform silicide formation was obtained across the wafer, and the resistivity of the Ni(SiGe:C) silicide layer was 24 μ/spl Omega//spl middot/cm. About 50-100 nm of lateral growth of silicide underneath the emitter pedestal was observed. DC and HF results with balanced f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> values of 41/42 GHz were demonstrated for 0.5×10μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> transistors.

94-GHz fT, 0.4-dB NFmin HBT with Optimized Si Cap and Extrinsic Base Using Blanket SiGeC Epitaxy

The profile design methodology of heterojunction bipolar transistors (HBTs) using a blanket SiGeC epitaxial layer is presented from the viewpoint of a Si cap and an extrinsic base design. Although important, it is difficult to optimize the intrinsic and extrinsic base regions of a HBT using blanket epitaxy since these regions are simultaneously grown and their profiles cannot be controlled independently. In accordance with the optimum Si cap thickness, extrinsic base implantation and cobalt silicidation were carried out to obtain a low base resistance and a high maximum oscillation frequency ( fmax). A cobalt silicide process for the extrinsic base was optimized to accommodate the Si cap thickness without forming highly resistive layers caused by a reaction between Ge and Co. This design led us to realize HBTs with a 94 GHz cutoff frequency ( fT) and an 81 GHz fmax, and a 0.4 dB NFmin at 2 GHz, which could be used for consumer electronic products operating within a 2–5 GHz frequency range.

Investigation of Compact Models for RF Noise in SiGe HBTs by Hydrodynamic Device Simulation

A comprehensive investigation of the SPICE and unified compact noise models is performed by comparison with the more fundamental hierarchical hydrodynamic device model. It is shown that the rather simple SPICE and unified compact noise models yield good results for frequencies up to 10 GHz for state-of-the-art SiGe HBTs with a low base resistance. The base noise resistance, a key parameter of the compact noise models turns out to be independent of frequency and bias. It can be well estimated based on the sheet resistance of the intrinsic and extrinsic base or with the modified circle-fit method. The unified model, which in comparison to the SPICE model considers in addition the finite transit time of shot noise, is found to be somewhat more accurate than the SPICE model, especially at higher frequencies and collector currents. But this is achieved at the expense of a transit time parameter which cannot be determined without accurate and detailed noise measurements or physics-based numerical simulations.

The behavior of Ti silicidation on Si/SiGe/Si base and its effect on base resistance and fmax in SiGe hetero-junction bipolar transistors

The relation between Ti silicidation and base resistance in SiGe hetero-junction bipolar transistors (HBT) was investigated. The Ti layer deposited on the Si/SiGe/Si base converted to Ti silicide during two-step annealing. The thickness of the Ti silicide, which was identified as the Ti(Si1-xGex) phase of uniform composition, abruptly increased over the annealing temperature of 650/850 °C, and as a result it accomplished a very low extrinsic base resistance. The Ti silicidation affected the base resistance of real devices (RB), which was extracted from simulating the electrical data of SiGe HBTs such as I –V curves, forward Gummel plots, forward current gain curves, and s-parameter plots. It was shown that the RB was compatible with the theoretical relation which included the small-signal unity-gain frequency (fT), the maximum oscillation frequency (fmax) and RB. fmax varied more sensitively with RB than fT, which was due to the inherent property of fmax being inversely proportional to √RB. The fmax of the SiGe HBT reached 47.4 GHz when Ti silicidation was performed at the annealing temperature of 650/850 °C. This silicidation condition is thought to be an appropriate temperature for Ti silicidation applicable to SiGe HBT fabrication. © 2001 Kluwer Academic Publishers

A novel lateral bipolar transistor with 67 GHz f/sub max/ on thin-film SOI for RF analog applications

In this paper, a novel lateral bipolar transistor on thin film silicon-on-insulator (SOI) is presented. With a small emitter size of 0.12/spl times/3.0 /spl mu/m/sup 2/, low base resistance of 270 /spl Omega/ due to a novel Co silicided base electrode and low base-collector parasitic capacitances of 1.4 fF due to SOI material, it achieves the highest f/sub max/ of 67 GHz among SOI bipolar transistors. Also, the low emitter-base capacitance of 1.5 fF and the low collector-substrate capacitance of 2.5 fF are realized. The transistor has a simple structure, which is fabricated with simplified processes without any new sophisticated technologies, excluding trench isolation and epitaxial base used in current bipolar transistors. This can lower the fabrication cost of transistors. We have demonstrated the possibility of lateral bipolar transistor on thin film SOI as next-generation device for RF analog applications.

AlGaN–GaN–AlInGaN induced base transistor

We have simulated an induced base transistor based on n-type GaN–AlGaN–GaN–AlInGaN heterostructure with a thin AlGaN emitter barrier and a thin GaN quantum well base. Our simulations show that such a majority carrier device should have a high collector current density, a low base resistance, a high current gain, and is expected to be a viable competitor to GaN-based heterostructure bipolar junction transistors.

Reduction of Base Resistance and Increase in Cutoff Frequency of Si Bipolar Transistor Using Rapid Vapor-Phase Doping

The shallow intrinsic base region of a double poly-Si self-aligned bipolar transistor was formed by rapid vapor-phase doping (RVD) in order to increase the high-frequency performance, compared to that provided by low-energy BF2 ion implantation. RVD produced a transistor with fT of 50-GHz and rb of 400-Ω. These parameters are 20% higher and 15% lower than those of a transistor produced by BF2 implantation. Low base resistance also led to an increase in the maximum oscillation frequency fmax to over 40 GHz in transistors with longer emitter. A two-dimensional profile simulation clarified that RVD can form a shallower intrinsic base profile and a deeper link base profile than those formed by BF2 ion implantation. These doping profiles made it possible to increase fT and fmax, and to reduce rb simultaneously.

AlGaAs/GaAs HBTs with extrinsic base regrowth

N–p–n abrupt AlGaAs/GaAs heterojunction bipolar transistors (HBTs) with a 500 Å-thick GaAs base, and regrown thick extrinsic base layers of p + AlGaAs/GaAs have been fabricated. The regrown extrinsic base layers allow easy contact to the base with low base resistance to achieve high f max. f max was improved by a factor of ∼2 with regrown base compared to conventional processing, up to a value of 45 GHz in these non-self-aligned devices. The extrinsic base regrowth was done at 500°C by MOMBE, which employed low-temperature in situ etch using tris-dimethylaminoarsenic to remove residual oxide from the surface before regrowth.

Simulation and design of InAlAs/InGaAs pnp heterojunction bipolar transistors

The performance capabilities of InP-based pnp heterojunction bipolar transistors (HBT's) have been investigated using a drift-diffusion transport model based on a commercial numerical simulator. The low hole mobility in the base is found to limit the current gain and the base transit time, which limits the device's cutoff frequency. The high electron majority carrier mobility in the n/sup +/ InGaAs base allows a reduction in the base doping and width while maintaining an adequately low base resistance. As a result, high current gain (>300) and power gain (>40 dB) are found to be possible at microwave frequencies. A cutoff frequency as high as 23 GHz and a maximum frequency of oscillation as high as 34 GHz are found to be possible without base grading. Comparison is made with the available, reported experimental results and good agreement is found. The analysis indicates that high-performance pnp InP-based HBT's are feasible, but that optimization of the transistor's multilayer structure is different than for the npn device.