Adaptive Loop Gain Research Articles

A 6.4–11 Gb/s Wide-Range Referenceless Single-Loop CDR With Adaptive JTOL

A referenceless single-loop clock and data recovery (CDR) with a 6.4–11-Gb/s capture range is presented. A dynamic bandwidth control (DBWC) technique for reducing the frequency-acquisition time and adaptive loop gain control (ALGC) for optimizing the jitter tolerance are described in detail. In addition, a cycle-slip detector (CSDET) with a consecutive-edge selector (CES) is proposed to improve the accuracy of the frequency detection. Fabricated in a 28-nm CMOS process, the proposed CDR has a frequency-acquisition time that is reduced by approximately 30% with the DBWC technique enabled. Also, the capture range is expanded by 1.1 Gb/s compared to the prior work due to improvement of the CSDET. The proposed ALGC technique based on jitter estimation is demonstrated with JTOL test results using PRBS15 input data with 0.28-UI ${_{PP}}$ random jitter and 1–100 MHz sinusoidal jitter.

Improving Rate of Convergence via Gain Adaptation in Multi-Agent Distributed ADMM Framework

In this paper, the Alternating Direction Method of Multipliers (ADMM) is investigated for distributed optimization problems in a networked multi-agent system. In particular, a new adaptive-gain ADMM algorithm is derived in a closed form and under the standard convex property in order to greatly speed up convergence of ADMM-based distributed optimization. Using Lyapunov direct approach, the proposed solution embeds control gains into weighted network matrix among the agents and uses those weights as adaptive penalty gains in the augmented Lagrangian. It is shown that the proposed closed loop gain adaptation scheme significantly improves the convergence time of underlying ADMM optimization. Convergence analysis is provided and simulation results are included to demonstrate the effectiveness of the proposed scheme.

On the Cross-Correlation Based Loop Gain Adaptation for Bang-Bang CDRs

This article describes the cross-correlation function as an alternative method to adapt loop gain in digital CDRs. Cross-correlation function inherent properties and their link with the cross-power spectral density help consolidating the adaptive loop gain technique, XCALG, for clock and data recovery systems that implement bang-bang phase detector. Considering the modulation of the loop gain due to jitter noise, previous works exploit the autocorrelation function at the output of the bang-bang phase detector as a proper indicator to track the system dynamics and perform loop gain adaptation. In contrast, we propose the XCALG as a new alternative to perform loop gain adaptation featuring better observability, less impact from jitter sources while keeping a safe phase margin. Theory behind the idea is enhanced, and the XCALG is demonstrated through behavioral system simulations. In addition, preliminary implementation costs of the cross-correlation function are discussed using a 65nm CMOS technology node.

An adaptive loop gain selection for CLEAN deconvolution algorithm

Radio interferometry significantly improves the resolution of observed images, and the final result also relies heavily on data recovery. The Cotton-Schwab CLEAN (CS-Clean) deconvolution approach is a widely used reconstruction algorithm in the field of radio synthesis imaging. However, parameter tuning for this algorithm has always been a difficult task. Here, its performance is improved by considering some internal characteristics of the data. From a mathematical point of view, a peak signal-to-noise-based (PSNR-based) method was introduced to optimize the step length of the steepest descent method in the recovery process. We also found that the loop gain curve in the new algorithmis a good indicator of parameter tuning. Tests show that the new algorithm can effectively solve the problem of oscillation for a large fixed loop gain and provides a more robust recovery.

A fast-locking bang-bang phase-locked loop with adaptive loop gain controller * * Project supported by the National Nature Science Foundation of China (Nos. 61331003, 61474108), the National Key Technology Research and Development Program of the Ministry of Science and Technology of China (No. 2016ZX03001002).

This paper proposes a fast-locking bang-bang phase-locked loop (BBPLL). A novel adaptive loop gain controller (ALGC) is proposed to increase the locking speed of the BBPLL. A novel bang-bang phase/frequency detector (BBPFD) with adaptive-mode-selective circuits is proposed to select the locking mode of the BBPLL during the locking process. Based on the detected results of the BBPFD, the ALGC can dynamically adjust the overall gain of the loop for fast-locking procedure. Compared with the conventional BBPFD, only a few gates are added in the proposed BBPFD. Therefore, the proposed BBPFD with adaptive-mode-selective circuits is realized with little area and power penalties. The fast-locking BBPLL is implemented in a 65 nm CMOS technology. The core area of the BBPLL is 0.022 mm2. Measured results show that the BBPLL operates at a frequency range from 0.6 to 2.4 GHz. When operating at 1.8 GHz, the power consumption is 3.1 mW with a 0.9-V supply voltage. With the proposed techniques, the BBPLL achieves a normalized locked time of 1.1 μs @ 100 MHz frequency jump. The figure-of-merit of the fast-locking BBPLL is −334 dB.

Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs

A loop gain adaptation technique is proposed, which optimizes the jitter tolerance (JTOL) of a 28 Gb/s phase interpolator (PI)-based clock and data recovery (CDR) circuit implemented in 28 nm CMOS. The technique increases the CDR’s loop gain to suppress the most jitter while monitoring the autocorrelation function of the bang-bang phase detector (BB-PD) output to prevent the CDR from becoming too underdamped. The proposed technique requires no knowledge of the CDR’s loop latency or input jitter characteristics.

Adaptive Gain Control Method of a Phase-Locked Loop for GNSS Carrier Signal Tracking

The global navigation satellite system (GNSS) has been widely used in both military and civil fields. This study focuses on enhancing the carrier tracking ability of the phase-locked loop (PLL) in GNSS receivers for high-dynamic application. The PLL is a very popular and practical approach for tracking the GNSS carrier signal which propagates in the form of electromagnetic wave. However, a PLL with constant coefficient would be suboptimal. Adaptive loop noise bandwidth techniques proposed by previous researches can improve PLL tracking behavior to some extent. This paper presents a novel PLL with an adaptive loop gain control filter (AGCF-PLL) that can provide an alternative. The mathematical model based on second- and third-order PLL was derived. The error characteristics of the AGCF-PLL were also derived and analyzed under different signal conditions, which mainly refers to the different combinations of carrier phase dynamic and signal strength. Based on error characteristic curves, the optimal loop gain control method has been achieved to minimize tracking error. Finally, the completely adaptive loop gain control algorithm was designed. Comparable test results and analysis using the new method, conventional PLL, FLL-assisted PLL, and FAB-LL demonstrate that the AGCF-PLL has stronger adaptability to high target movement dynamic.

The adaptive-loop-gain adaptive-scale CLEAN deconvolution of radio interferometric images

CLEAN algorithms are a class of deconvolution solvers which are widely used to remove the effect of the telescope Point Spread Function (PSF). Loop gain is one important parameter in CLEAN algorithms. Currently the parameter is fixed during deconvolution, which restricts the performance of CLEAN algorithms. In this paper, we propose a new deconvolution algorithm with an adaptive loop gain scheme, which is referred to as the adaptive-loop-gain adaptivescale CLEAN (Algas-Clean) algorithm. The test results show that the new algorithm can give a more accurate model with faster convergence.

An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang–Bang Phase-Frequency Detection

An all-digital phase-locked loop with a bang-bang phase-frequency detector (BBPFD) that tracks the optimum loop gain for minimum jitter is proposed. The autocorrelation of the output of BBPFD indicates whether the bang-bang PLL operates in the nonlinear regime or the random noise regime. An adaptive loop gain controller continuously evaluates the autocorrelation of the BBPFD output and adjusts the loop gain to make the autocorrelation zero. The digital loop filter operates at higher than the reference clock frequency to reduce the loop latency and to mitigate the resolution of the digitally controlled oscillator. The prototype chip has been fabricated in a 65-nm CMOS process. The core consumes 5 mW at 2.5 GHz and exhibits root-mean-square jitter of 1.72 ps.

A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy

A Bang-Bang Clock and Data Recovery (CDR) with adaptive loop gain strategy is presented. The proposed strategy enhances CDR jitter performance even if jitter spectrum information is limited a priori. By exploiting the inherent hard-nonlinearity of Bang-Bang Phase Detector (BBPD), the CDR loop gain is adaptively adjusted based on a posteriori jitter spectrum estimation. Maximizing advantages of analog and digital implementations, the proposed mixed-mode technique achieves PVT insensitive and power efficient loop gain adaptation for high speed applications even in limited ft technologies. A modified CML D-latch improves CDR input sensitivity and BBPD performance. A folded-cascode- based Charge Pump (CP) is proposed to minimize CP latency. The 5 G/10 G CDR prototype is fabricated in 0.18 μm CMOS technology to demonstrate the effectiveness of the proposed techniques for applications with high ratio of data-rate to ft. The proposed CDR recovers data with BER <; 2·10-13 and generates only 1.04 ps RMS and 7.5 ps peak-peak jitter. Jitter Tolerance (JTOL) test shows that the proposed CDR enhances low frequency jitter tracking and high frequency jitter filtering simultaneously for various jitter profiles. The CDR power consumption is 110.6 mW where only 3.9 mW is used for loop gain adaptation circuitry.

A 0.3–1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller

A 0.3–1.4 GHz all-digital phase locked loop (ADPLL) with an adaptive loop gain controller (ALGC), a 1/8-resolution fractional divider and a frequency search block is presented. The ALGC reduces the nonlinearity of the bang-bang phase-frequency detector (BBPFD), reducing output jitter. The fractional divider partially compensates for the large input phase error caused by fractional-N frequency synthesis. A fast frequency search unit using the false position method achieves frequency lock in 6 iterations that correspond to 192 reference clock cycles. A prototype ADPLL using a BBPFD with a dead-zone-free retimer, an ALGC, a fractional divider, and a digital logic implementation of a frequency search algorithm was fabricated in a 0.13- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\hbox {m}}$</tex></formula> CMOS logic process. The core occupies 0.2 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\hbox {mm}}^{2}$</tex> </formula> and consumes 16.5 mW with a 1.2-V supply at 1.35-GHz. Measured RMS and peak-to-peak jitter with activating the ALGC are 3.7 ps and 32 ps respectively.

Low-jitter digital timing recovery techniques for cap-based vdsl applications

In this paper, a digital timing recovery technique for carrierless amplitude and phase modulation (CAP)-based very-high-speed digital subscriber line (VDSL) applications is presented. A digital spectral line method is proposed for the timing tone extraction. It avoids the bandwidth expansion normally caused by the nonlinear property of the timing tone extraction block, and lowers the required sampling clock frequency. Also, an adaptive loop gain control scheme is proposed to reduce the timing jitter, simultaneously achieving both fast locking and low steady-state jitter. A prototype timing recovery circuit in a 0.35-/spl mu/m CMOS technology achieves 12.02-ps and 86-ps rms and peak-to-peak jitter, respectively, at 40-MHz operation. This is equivalent to about 0.1% of the symbol rate, and suitable for VDSL applications. The prototype IC consumes about 55 mW with a 3.0-V power supply.

Vehicular speed response PLL using square‐law circuits

AbstractIn this paper, we propose using a square‐law loop circuit that does not require a pilot signal in a vehicular speed response phase‐locked loop (PLL) and study its performance. In the PLL performance in the fading transmission path in mobile communications, a vehicular speed response PLL improves the PLL performance by using a directional antenna to lengthen the fading period and by providing frequency offset information generated in response to the vehicular speed to the PLL. Compared with a PLL using a conventional square‐law circuit, the proposed scheme effectively uses the cancellation effect of the frequency offset and the loop gain adaptation based on the vehicular speed response to obtain substantial improvement in the bit error rate. A substantial improvement is exhibited, particularly in an environment having a highfDT. © 2002 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 85(8): 22–29, 2002; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.1109

Performance of an Adaptive Array Processor Subjected to Time-Varying Interference

Array processors for passive detection of directional wide-band Signals are commonly used in sonar, seismic work, and radio astronomy. The performance of such processors is degraded by directional noise sources referred to as interferences and adaptive processors to eliminate the effect of interferences have been used for many years. The issue addressed in this paper is movement of the interference and the effect that this has on adaptive loop design. The processor considered in the paper is an array of adjustable FIR filters using the Widrow LMS algorithm to adjust the filter weights. Changes in interference patterns affect both the covariance matrix of the observed signal and the optimum weight vector. For the purposes of this paper the optimum weight vector is modelled as an independent-increment process. This model permits the rigorous derivation of the optimum adaptive-loop gain parameter and of worst-case performance. In general it is found. that interference movement results in two error components: a gradient-noise component and a tracking component. Increases in adaptive loop gain decrease the tracking component but increase the gradient-noise component. Thus for a given set of interference-motion statistics an optimum gain can be found.

Stability of model-reference systems with random impulsive inputs

The stability of the gain-adjusting loop of a simple model-reference adaptive-control system is investigated. The input to system and model is a sequence of impulses of random magnitude. The resulting behaviour is determined by an infinite product, and from this a necessary and sufficient criterion for the stability of the adaptive-loop gain is deduced.