Logic Synthesis Tools Research Articles

Designing an asynchronous microcontroller using Pipefitter

This paper discusses how Pipefitter, a tool chain that implements a fully automated synthesis flow for asynchronous circuits, can be used to design a simple asynchronous microcontroller. The use of register transfer level (RTL)-like Verilog hardware description languages (HDL) as the input format makes the first steps of the design flow (i.e., specification and simulation) very easy for the designer. Pipefitter directly synthesizes the control unit as a hazard-free standard cell netlist, uses a genetic algorithm to perform binding and multiplexer optimization for the datapath and allows the user to manually specify the binding. It also produces a synthesizable Verilog specification for the datapath, as well as a set of scripts driving both its synthesis and timing analysis by state-of-the-art commercial synchronous RTL and logic synthesis tools. The automated insertion of matched delays completes the logic design, and hands off the netlist to the standard cell-based layout tools. The example presented in this brief, shows how Pipefitter can be effectively used for the design of asynchronous application specific integrated circuits.

Overview of a compiler for synthesizing MATLAB programs onto FPGAs

This paper describes a behavioral synthesis tool called AccelFPGA which reads in high-level descriptions of digital signal processing (DSP) applications written in MATLAB, and automatically generates synthesizable register transfer level (RTL) models and simulation testbenches in VHDL or Verilog. The RTL models can be synthesized using commercial logic synthesis tools and place and route tools onto field-programmable gate arrays (FPGAs). This paper describes how powerful directives are used to provide high-level architectural tradeoffs for the DSP designer. Experimental results are reported on a set of eight MATLAB benchmarks that are mapped onto the Xilinx Virtex II and Altera Stratix FPGAs.

Synthesis of Single/Dual-Rail Mixed PTL/Static Logic for Low-Power Applications

We present single- and dual-rail mixed pass-transistor logic (PTL) synthesis method based on genetic search and compared the results with their conventional static CMOS counterparts synthesized using a commercial logic synthesis tool in terms of area, delay, and power in an experimental 0.1- and 0.13-/spl mu/m CMOS technologies as well as a 0.13-/spl mu/m floating-body partially depleted silicon-on-insulator (PDSOI) process. The proposed synthesis method first performs a search for possible matches between a logic structure and a set of predefined PTL/static logic gates using binary decision diagrams (BDDs). The unique contribution of our approach is the use of a genetic algorithm to determine the best mixture of PTL and static cells based on area and power. Our experimental results demonstrate that both single- and dual-rail mixed PTL circuits synthesized using the proposed mixed PTL/CMOS synthesis method outperforms their static counterparts in delay and power in bulk CMOS as well as silicon-on-insulator (SOI) CMOS technologies. The average power of single- and dual-rail mixed PTL/Static ISCAS'85 benchmark circuits using the proposed method in the 0.1-/spl mu/m bulk CMOS process are 73% and 50% better than their static counterparts with performance gains of 5% and 10%, respectively.

Globally updated mesochronous design style

In large-scale and high-speed digital systems, global synchronization has frequently been used to protect clocked I/O from data failure due to metastability. Synchronous design styles are widely used, easy to grasp and to implement, and also well supported by logic synthesis tools. There are many drawbacks with global synchronization. Most important is the relationship between physical size and maximum clock frequency, which will approach its limit as clock frequency and system size increase simultaneously. The purpose of this proposed Globally Updated Mesochronous (GUM) design style is to overcome those drawbacks by identifying all global signal links in the system and adding synchronization circuits to these. System level simplicity, inherited from synchronous design and its tool support, is retained. In this paper, the GUM design style is described, analyzed, and demonstrated. Experimental results from a large-scale high-speed system using three 0.8-/spl mu/m BiCMOS chips are given. The GUM design style is scaleable and suitable for future system-on-chip applications both on and among chips.

Multilevel logic synthesis using hybrid pass logic and CMOS topologies

The development is described of an automated logic synthesis tool, BDDMAPII, which has the capability of utilising a new multilevel mapping algorithm. It has been designed specifically with a reduced cell library consisting of pass transistor multiplexer-based cells in conjunction with traditional CMOS circuits. These cells were developed based on TSMC's 0.18μ-CMOS technology. A subset of MCNC91 benchmark circuits are used to evaluate the synthesis tool, and the results are compared to those generated by Design Analyzer, a commercial tool from Synopsys Inc. An improvement of an average of 21% in power–delay product was achieved when using the proposed hybrid cell library.

A Ring Architecture Strategy for BIST Test Pattern Generation

This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under test (CUT), i.e., no test point insertion. The set of patterns generated by a pseudo-random pattern generator, e.g. a Linear Feedback Shift Register (LFSR), is transformed into a new set of patterns that provides the desired fault coverage. To transform these patterns, a ring architecture composed by a set of masks is used. During on-chip test pattern generation, each mask is successively selected to map the original pattern sequence into a new test sequence. We describe an efficient algorithm that constructs a ring of masks from the test cubes provided by an automatic test pattern generator (ATPG) tool. Moreover, we show that rings of masks are implemented very easily at low silicon area cost, without requiring any logic synthesis tool; a combinational mapping logic corresponding to the masks is placed between the LFSR and the CUT, together with a looped shift register that acts as a mask selecting circuit. Experimental results are given at the end of the paper, demonstrating the effectiveness of the proposed approach in terms of area overhead, fault coverage and test sequence length. Note that this paper is an extended version of [1].

Synthesis of single-output space compactors for scan-based sequential circuits

This paper addresses the problem of space compaction of test responses of combinational and scan-based sequential circuits. In a general circuit, compaction of output space to a single output with zero-aliasing cannot always be achieved by earlier known approaches. In this work, it is shown that given a precomputed test set T, the test responses at the functional outputs of any arbitrary circuit-under-test (CUT) can be compacted to a single periodic output, with guaranteed zero aliasing. All the errors that are produced by T at the outputs of the CUT will also appear at the output of the compactor. The method is independent of the fault model and the structure of the CUT and uses only the knowledge of the test set T and the corresponding fault-free responses. A new concept of distinguishing outputs and a characteristic function is used to design the compactor. The test vectors in T are appropriately ordered to optimize the compactor logic, which to achieve zero-aliasing uses a test pattern counter to designate the sequence of test application and a special code checker. A design procedure is described to synthesize the compactor using logic synthesis tools, and relevant experimental results on hardware overhead for several benchmark circuits are presented. It is further shown that the overhead can be significantly reduced if the constraint of exact zero aliasing is slightly relaxed.

Synthesis of low-power CMOS circuits using hybrid topologies

This paper describes the development of a logic synthesis tool, BDDMAP, designed specifically to work with a reduced set cell library consisting of a combination of pass logic and standard CMOS topologies. Delay and statistical power models have been developed for pass logic cells to be used in our optimization algorithm. MCNC benchmarks were used to evaluate the tool and the proposed circuit topology against the results obtained from Synopsys’ Design Analyzer. An improvement of 34.5% in power-delay product was achieved when using our cell library and 42.3% when using a standard CMOS library.

An efficient frame memory interface of MPEG-2 video encoder ASIC chip

This paper presents an efficient frame memory interface of MPEG-2 video encoder which is accomplished in not only reducing interface buffer size through efficient memory map organization and access timing schedules but also avoiding unnecessary small size buffers and simplifying their control circuits. In this design, 0.5 /spl mu/m CMOS TLM (triple layer metal) standard cells are used as design libraries, and VHDL simulator and logic synthesis tools are used for hardware design and verification, and the hardware emulator that is a C-language model of the proposed architecture is exploited for various test vector generation and functional verification. The improved frame memory interface module takes about 58% less hardware area than the previous design (Kim et al. 1997), and results in reducing the total hardware area of the video encoder ASIC chip up to 24.3%. We also reduced the random memory accesses to save the power consumption caused by the transition of the system-level I/O buses.

PTM: Technology mapper for pass-transistor logic

The pass-transistor mapper (PTM) is reported; this is a logic synthesis tool specifically designed for pass-transistor-based logic library that has only three basic cells. It exploits the close relationship between a binary decision diagram (BDD) representation of logic and the structure of pass-transistor logic cells to ensure efficient technology mapping. BDD-variable order optimisation is achieved through a genetic algorithm with dynamic parameters. Unlike a previous system for pass-transistor logic, PTM integrates both synthesis and logic optimisation in one step and can be used for large logic functions. Results from using PTM on a large set of benchmarks are analysed using the MCNC CMOS cell library and are found to be promising.

A BDD-based verification method for large synthesized circuits

Nowadays, logic synthesis tools are widely used to optimize and implement digital systems. Verifying the correctness of the generated circuits is an important practical problem. We present a new formal verification method for large synthesized circuits. It combines the use of binary decision diagrams (BDDs) with techniques to exploit the structural similarities of the circuits under comparison. These similarities are detected automatically. We show that the proposed method significantly extends the capability of BDD-based methods to verify large synthesized circuits.

Effective Coupling Between Logic Synthesis and Layout Tools for Synthesis of Area and Speed-Efficient Circuits

Traditionally logic synthesis and layout tools optimize designs without interaction between them. Lack of communication between the two tools often results in inferior post-layout circuit implementations. This paper presents three aspects of coupling synthesis with layout to minimize post-layout area and delay of circuits. It presents two new techniques for computing net-weights based on timing slacks, and shows how performance improvement with little overhead in area can be achieved. Secondly, it presents a novel idea of exploiting logic equivalence information in circuits to minimize circuit area and delay during layout. An algorithm for computing logic equivalence classes and performing net swapping using the equivalence classes during layout is described. Lastly, it shows the sensitivity of post-layout delays of circuits to wiring models used in synthesis and demonstrates how resynthesis techniques can be effectively used to generate good post-layout implementation. Significant reductions in post-layout area and delay on several industrial designs have been observed.

Automatic generation of command level simulation model of a processor from rt level description

AbstractIn designing a digital circuit with a microprocessor, there are several simulation levels. Using a logic synthesis tool and a layout synthesis tool, a lower‐level simulation model can be generated from a design RT level described in HDLs. There is trade‐off between accuracy and speed of simulations. A lower‐level simulation model can simulate more accurately. There is little support for generating high‐level simulation models in which a human designer is required. In this paper, an algorithm is proposed for high‐level simulation model generation and experimental results are shown.

A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach

This paper presents a method and an algorithm for generation of a parallel multiplier, which is optimized for speed. This method is applicable to any multiplier size and adaptable to any technology for which speed parameters are known. Most importantly, it is easy to incorporate this method in silicon compilation or logic synthesis tools. The parallel multiplier produced by the proposed method outperforms other schemes used for comparison in our experiment. It uses the minimal number of cells in the partial product reduction tree. These findings are tested on design examples simulated in 1 /spl mu/ CMOS ASIC technology.

DRS - Derivational Reasoning System: A Digital Design Derivation System for Hardware Synthesis

Formal methods provide a mathematical basis for eliminating design flaws during the specification and validation phase of the design cycle. Derivation Systems, Inc. IS developing a formal design tool called, DRS (Derivational Reasoning System), that implients a mathemattial formalism for constructing digital. hardware systems from high-level specifications. The system integrates alternate forms of formal reasoningbto support the analytical and generative reasoning that takes place in engineering practice. The design paradigm mtegrates a powerful derivation engine with existing theorem provers and logic synthesis tools to provide a practical tool for realizing hardware

The impact of cell library characteristics on area, speed and power consumption of CMOS circuits

Technology mapping is one of the major steps in the synthesis process of integrated circuits. Efficient algorithms have been proposed in the recent past to optimize the number of cells required to implement a given design, to increase its speed, and to reduce its power dissipation. However, not enough effort has been spent in studying the relationship between the quality of the circuit produced by the logic synthesis tool and the cell library used to perform the mapping. In this paper we present experiments on technology mapping that show how the design of the cell library can influence area, speed and power consumption of the synthesized circuit.

Verifying a logic-synthesis algorithm and implementation: a case study in software verification

We describe the verification of a logic synthesis tool with the Nuprl proof development system. The logic synthesis tool, Pbs, implements the weak division algorithm. Pbs consists of approximately 1000 lines of code implemented in a functional subset of Standard ML. It is a proven and usable implementation and is an integral part of the Bedroc high level synthesis system. The program was verified by embedding the subset of Standard ML in Nuprl and then verifying the correctness of the implementation of Pbs in the Nuprl logic. The proof required approximately 500 theorems. In the process of verifying Pbs we developed a consistent approach for using a proof development system to reason about functional programs. The approach hides implementation details and uses higher order theorems to structure proofs and aid in abstract reasoning. Our approach is quite general, should be applicable to any higher order proof system, and can aid in the future verification of large software implementations. >

An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis

A novel way of implementing the leading zero detector (LZD) circuit is presented. The implementation is based on an algorithmic approach resulting in a modular and scalable circuit for any number of bits. We designed a 32 and 64 bit leading zero detector circuit in CMOS and ECL technology. The CMOS version was designed using both: logic synthesis and an algorithmic approach. The algorithmic implementation is compared with the results obtained using modern logic synthesis tools in the same 0.6 /spl mu/m CMOS technology. The implementation based on an algorithmic approach showed an advantage compared to the results produced by the logic synthesis. ECL implementation of the 64 bit LZD circuit was simulated to perform in under 200 ps for nominal speed. >

Polynomial time testability of circuits generated by input decomposition

Considers polynomial time testability of combinational circuits generated by input decomposition, especially those generated by the logic synthesis tool FACTOR. First, the complexity of the fault detection problem in this class of circuits is explored using a stuck-at fault model. An O(2/sup k/m) algorithm for detecting a single stuck-at fault is given that is faster than the O(16/sup k/m), previously reported best algorithm proposed by Fujiwara(1990), where k is the number of inputs in a subcircuit and m the number of signal lines in the circuit. Efficient, polynomial time algorithms are described for generating a test set for all single stuck-at faults in the circuit. The basic strategy is to eliminate backtracks during line justification by constructing tables or vector sets in each subcircuit, which makes the fault propagation procedure very simple and eventually results in an efficient test generation procedure. This presentation of efficient polynomial time test generation algorithms for FACTOR-generated circuits is important, since it shows that it is possible to synthesize circuits that are optimized for area and are polynomial time testable at the same time. >

Computing the initial states of retimed circuits

Retiming is an optimization technique for sequential circuits which consists in modifying the position of latches relative to blocks of combinational logic in order to minimize the maximum propagation delay between latches or to meet a given delay requirement while minimizing the number of latches. If the initial state of the circuit is meaningful, one must compute an equivalent initial state for the retimed circuit after retiming. The authors present a simple linear time algorithm to compute a correct initial state for a retimed circuit that can be used whenever the initial state of the original circuit satisfies a simple condition. If this condition is not originally satisfied, it is shown how it can be automatically enforced by a logic synthesis tool with no need for user intervention.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>