Logic Synthesis Tools Research Articles

An MPGA-like FPGA

The CP20K series of field-programmable gate array (FPGA) chips is described. Consisting of an array of individual CMOS transistors and small logic elements linked via antifuse-programmable interconnections to form large functional blocks, the CP20K closely mimics the flexibility and capacity of a mask-programmable gate array (MPGA). It is shown that the chip's fine-grained architecture makes it easy to use logic synthesis tools because area and performance can be traded off exactly as in MPGA logic synthesis.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Synthesis tools help teach systems concepts in VLSI design

The VLSI project class at Princeton University has been redesigned, using modern logic and layout synthesis tools, to emphasize system design issues. The design methodology taught in the class allows students to build larger designs; it also allows them to learn, by redesign, how to trade off layout, circuit, logic, and architectural design problems. Two synthesis tools were developed (based on the Oct tool set from UC Berkeley) to generate standard cell layouts: one which takes as input finite-state machine transition tables; and one which generates netlists using C programs. The author describes; what is important for students to learn in a VLSI design class; the design methodology developed to teach this curriculum through a design project; and the CAD tools used to support this design methodology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Engineering software-more logic synthesis for ASICs

Computer-aided design (CAD) tools that reduce application-specific integrated circuit (ASIC) development time are examined. The use of hardware description languages to ease the data entry tasks of ASIC designers is discussed. Coupling logic synthesis tools to layout tools is considered. Limitations of logic synthesis are addressed, and some features of intelligent synthesis tools are described. >

The Olympus synthesis system

A description is given of the Olympus synthesis system for digital design, a vertically integrated set of tools for multilevel synthesis, technology mapping, and simulation. The system includes behavioral, structural, and logic synthesis tools, and provides technology mapping and simulation. Since it is targeted for semicustom implementations, its output is in terms of gate netlists. Instead of supporting placement and routing tools, Olympus provides an interface to standard physical design tools. The system supports the synthesis of ASICs (application specific integrated circuits) from behavioral descriptions written in a hardware description language called HardwareC. Two internal models represent the hardware at different levels of abstraction and provide a way to pass design information among different tools. Olympus has been used to design three ASIC chips, and has been tested against benchmark circuits for high-level and logic synthesis.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>