Abstract
A description is given of the Olympus synthesis system for digital design, a vertically integrated set of tools for multilevel synthesis, technology mapping, and simulation. The system includes behavioral, structural, and logic synthesis tools, and provides technology mapping and simulation. Since it is targeted for semicustom implementations, its output is in terms of gate netlists. Instead of supporting placement and routing tools, Olympus provides an interface to standard physical design tools. The system supports the synthesis of ASICs (application specific integrated circuits) from behavioral descriptions written in a hardware description language called HardwareC. Two internal models represent the hardware at different levels of abstraction and provide a way to pass design information among different tools. Olympus has been used to design three ASIC chips, and has been tested against benchmark circuits for high-level and logic synthesis.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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