Abstract
Computer-aided design (CAD) tools that reduce application-specific integrated circuit (ASIC) development time are examined. The use of hardware description languages to ease the data entry tasks of ASIC designers is discussed. Coupling logic synthesis tools to layout tools is considered. Limitations of logic synthesis are addressed, and some features of intelligent synthesis tools are described. >
Full Text 
Sign-in/Register to access full text options
Sign-in/Register to access full text options 
Published version (
Free)
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
