Integrating logic synthesis into a full chip ASIC design system

Abstract

How logic synthesis can be integrated in a full-chip ASIC (application-specific integrated circuit) design system to maximize the design process is discussed. The discussion is based around the specifics of the ChipCrafter ASIC design system. It is shown that the logic synthesis can speed the implementation of glue or control logic and allow the user to explore the design space for optimal tradeoffs between area and delay. When coupled with a full-chip design system, the synthesis tools can weigh detailed information about actual area and delay, including interconnect area and loading, for more accurate design tradeoffs. Logic blocks account for only a portion of most designs. It is not enough to optimize the logic isolation. An integrated system, which can consider the logic in the context of the entire design, may be able to achieve a significant improvement over chip layout and logic synthesis accomplished separately. >