Logic Simulation Research Articles

Guest editorial: Smart communications and networking: architecture, applications, and future challenges

Guest editorial: Smart communications and networking: architecture, applications, and future challenges

Design and implementation of a nano magnetic logic barrel shifter using beyond-CMOS technology

Abstract Bit manipulation plays a significant role in high-speed digital signal processing (DSP) and data computing systems, and shift and rotation operations are crucial functions in it. In general, barrel shifters are used to perform these operations effectively. Nano magnetic logic circuits are among the promising beyond-CMOS alternative technologies for the design of high-speed circuits. Most of the existing circuits that have been developed using nano magnets are combinational circuits. In this work, a barrel shifter is implemented and realised using in-plane nano magnetic logic. The proposed design is the first of its kind nano magnetic logic circuit. The nano magnetic logic circuit implementation, layout generation, simulation, and validation were performed using the ToPoliNano and ModelSim tools. The logical equivalent design was synthesised and evaluated using the Synopsys Design Compiler tool. The proposed barrel shifter was realised using majority logic has 1769037 nano magnets with a boxing area of 481 × 13104 µm2 and 3276 clock zones after optimisation with the Barycenter algorithm. The proposed barrel shifter realised using Boolean logic has 315276 nano magnets with a boxing area of 265 × 5028 µm2 and 1257 clock zones after optimisation with the Barycenter algorithm. The proposed design results demonstrate that complex systems can be developed using nano magnetic logic by combining combinational and sequential circuits.

전기차용 BLDC 와이퍼 전동기의 소음 저감을 위한 최적의 도통각 제어

This paper proposes optimal conduction angle for noise reduction in xEV BLDC wiper motors. Fuzzy logic simulation is performed to review the noise influences by conduction angle. After confirming that the current and torque ripple change according to the parameter change, and the optimized control method and parameters from the simulation to the controller is reflected. A test is conducted to reduce noise in a specific frequency range. Noise influences are verified through Fast Fourier Transform analysis on current wave forms and noise test results.

MBSE for Civil Aircraft Scaled Demonstrator Requirement Analysis and Architecting

A civil aircraft scaled demonstrator is an unmanned aerial vehicle (UAV) obtained by reducing the geometry of a civil aircraft by an equal scale and simplifying the airframe and airborne subsystems. Due to the low development cost and flight risk of scaled demonstrators, flight tests with demonstrators are an attractive way to assess the reliability and effectiveness of new configurations and/or technologies available for civil aircraft. Nevertheless, engineers still hope to reduce the development cycles and costs of demonstrators to evaluate their multiple civil aircraft design solutions through flight tests in a short period of time. Model-based systems engineering (MBSE) is a formalized requirement and architecture modeling method which is a useful tool in aircraft design. However, no existing MBSE framework has been found suitable for the development of demonstrators due to their unique features. In this paper, an MBSE approach for civil aircraft scaled demonstrator is proposed based on the MagicGrid methodology and the existing technical process for the demonstrator. This approach formalizes the requirement analysis and architecting for demonstrators via system modeling language (SysML). Meanwhile, the stakeholders of civil aircraft scaled demonstrators are identified, and a requirement ontology and modeling standard are established according to existing demonstrator development practice. Then, a case study is performed through a hybrid power demonstrator which carries a hydrogen fuel cell as the main power supply, a set of solar cells, and two lithium cells. The requirement traceability and verifiability are examined, and a logic simulation is executed for architecture, which shows the feasibility of applying the MBSE approach for the development of civil aircraft scaled demonstrators.

Design and simulation of optical logic gates at ultra high speed of 200 Gb/s employing single SOA

For Future high speed optical networking and switching applications there is a need of realization of high-speed all-optical devices and functionalities which are capable of performing processing at high bit rate. So, this study has come along by means of implementation of all-optical logic gates at ultra-high speed of 200 Gb/s. Optical AND and OR functionality is attained with the help of two data signals along with two pump signals using single SOA. While NOT gate is achieved with single data source along with the two pump signals in single SOA structure. Thus, the attainment of all-optical logics at ultra-high speed of 200 Gb/s with single SOA will bring high speed operation in the field of all-optical data handling and processing.

Smart Monitoring System for Chronic Kidney Disease Patients based on Fuzzy Logic and IoT

A Chronic Kidney Disease (CKD) monitoring system was proposed for early detection of cardiovascular disease (CVD) and anemia using Fuzzy Logic. To determine the heart rate and blood oxygen saturation, the proposed model was simulated using MATLAB and Simulink to handle ECG and PPG inputs. The Pan-Tompkins method was used to determine the heart rate, while the Takuo Aoyagi algorithm was used to assess blood oxygen saturation levels. The findings show that the ECG recorded using the CKD model has all of the characteristics of a typical ECG wave cycle, but with reduced signal degradation in the 0.8–1.3mV region. The heart rate signal processing yielded findings between 78 and 83 beats per minute is within the range of the supplied heart rate. Takuo Aoyagi's pulse oximeter simulation generated the same findings. For real-time verification, the proposed model was implemented in hardware using ESP8266 32-bit microcontroller with IoT integration via Wireless Fidelity for data storage and monitoring. In comparison with the Fuzzy Logic simulation done on MATLAB and Simulink, the CKD monitoring device has 100% accuracy in patient status detection. The CKD monitoring system has an overall accuracy of 99% in comparison with a commercial fingertip pulse oximeter.

Development of a general purpose First-In-First-Out (FIFO) core

First-In-First-Out cores (FIFOs) are memory storage elements that are used in digital systems for buffering data through a system for later processing. This paper presents the design and implementation of a General Purpose FIFO Core which allows adjustment of the capacity along with the size of each data word. Status indicators were provided to indicate whether or not the FIFO was empty, half-full, or full. The number of data words stored in the FIFO was also indicated by designated output ports of the system. A status flag was also available to indicate when the size reached a predetermined threshold value. A separate interface was provided that allowed the data at any address to be accessed for reading. It was also possible to write a data word to the back of the FIFO while another data word was read from the front simultaneously. The FSM-D architectural model was applied to the design of the FIFO Core and the implementation was done in VHDL using the Xilinx ISE 14.7. The implemented core was simulated using ISim Logic Simulator of the Xilinx ISE platform, and it was found that the system core behaved as specified by the test cases.

Gate-oxide-short defect analysis and fault modeling in FinFETs

FinFET has caused new challenges in reliable device testing due to its three-dimensional structure and reduced critical dimensions. Accurate defect modeling and generation of reliable fault models are essential to create realistic set of test patterns to detect defects. Cell-Aware Test (CAT) has significantly improved the detection of cell-internal defects in MOSFET-based circuits. However, the defect models utilized are obtained based on the defects injected at the layout level and represented by fixed lumped passive components that cannot reflect the true defect nature in the complex 3D structure of FinFET. Gate-oxide-short (GOS) is one of the defects that has significant impact on circuit reliability. This paper focuses on the 3D physical device structure, rather than the layout. The analysis is based on the 3D bulk FinFET template provided by Synopsys. We have performed DC and transient simulations on defective FinFETs with various defect locations and sizes in the Sentaurus TCAD environment. The comprehensive investigation of the GOS defect has led to the development of accurate defect models. These models are applied as Verilog-A modules in circuit-level simulation of complex logic gates such as And-Or-Invert (AOI) and 3:1 Multiplexer (MUX). We have also extracted the HSPICE model parameters for the FinFET template based on the BSIM-CMG local extraction procedure. The proposed fault modeling methodology is compared to the existing CAT-based approach and demonstrated its superiority. Our methodology is not limited to standard library cells, as the defect models are developed at the device 3D structure instead of the layout.

Parallel Comparator based voltmeter using Single Electron Tunneling Transistor

By manipulating an electron that tunnels the tunnel junction of a single electron transistor, one will be able to reach a standard output logic “1” or logic “0”. The operation of the Single Electron Transistor (SET) is depending upon the bias voltage as well as the input signal(s). By varying the input voltage levels of a SET, the output voltage levels can significantly be changed on the basis of tunneling of an electron whether tunneling happened or not. As our concentration is the measuring of an unknown voltage, we are to implement a voltmeter system to provide a digital output of 3 bits whenever an unknown input voltage is kept in touching in the input terminal. A reference/standard voltage (say 8mV) will be connected in series with eight resistances ( 8 Rs) for the purpose of making a seven threshold voltages, for 7 comparators, in an ascending order of values from ground to reference voltage for seven comparators which are used in this present work. The voltmeter implemented consists of (i) a voltage divider, (ii) a set of seven comparators, (iii) seven Exclusive-OR gates and (iv) three 4-input OR gates. The concepts of implementing “Parallel Comparator based voltmeter” is discussed in two ways (i) by classical block diagram and (ii) using Single electron transistor based circuit. The measuring of an input analog voltage will not be the same as the digital output value. A 3-bit output indicates that the input analog voltage must lie on within a particular small range of voltage. The encoder circuit which is connected to the outputs of the comparators is hard to construct whenever the three terminals output are expressed with the output variables (Wi) of the comparators. For simple and user-friendly circuit, the outputs (Wi) of the comparators are modified to Di variables so as to get the same 3-bit encoder/voltmeter output. For this purpose, 7 extra component called 2-input XORs based on SET are used. Seven such XORs are set, and the output of them are passed to three 4-input OR gates according to the required logic expressions. It is found that all the output data of the voltmeter are coherently matched with the theoretical aspects. Processing delays are found out for all circuits. Power consumptions of all of them are shown in tabular and graphical forms. All the circuit we are intending to make are provided in due places with their logic circuit or simulation set and the simulation results are provided as well. Different truth tables are given for keeping track of whether input-output relationships matches with the theoretical results. We have thought of whether the present work circuits are faster or slower than the circuits of CMOS based-circuits. The power consumed at the time of tunneling event for a circuit is measured and sensed that it exists in the range between 1×10^(-18) Joules to 22×10^(-18)Joules which is very small amount. All the combinational circuits presented in this work are of SET-based.

Design and simulation of all-optical logic gates based on two-dimensional photonic crystals

Design and simulation of all-optical logic gates based on two-dimensional photonic crystals

A PUF‐based lightweight authentication and key agreement protocol for smart UAV networks

With the advancement of information technology and the reduction of costs, the application of unmanned aerial vehicle (UAV) has gradually expanded from the military field to the industrial field and civilian field. It brings great convenience to people in surveillance, detection, transportation, emergency rescue etc. However, UAVs usually work in harsh natural environments, and their communication security confronts various challenges. Due to UAVs' limited resources, such as computing capability, storage space, and energy, traditional security protection schemes based on complex cryptographic algorithms are not suitable for UAV systems directly. Therefore, a two-stage lightweight identity authentication and key agreement protocol for UAV is proposed in this paper. The entire process only uses hash and XOR operations, which significantly improves the authentication efficiency. Simultaneously, the physical unclonable function (PUF) is introduced and embedded into the UAV hardware to ensure UAV network communication security when a UAV suffers a physical capture attack. In the paper, the security of the proposed protocol is proved with Burrows–Abadi–Needham (BAN) logic, Real-or-Random (ROR) model, and AVISPA simulation tools. An informal security analysis is also provided to illustrate that the protocol satisfies the security requirements of UAV networks. Finally, the protocol is compared with other existing protocols regarding function properties, computation cost, and communication cost, which shows that the proposed protocol has effectiveness and practicality.

Efficient Digital Waveform Compression Method for Logic Simulation of Integrated Circuits

<p indent=0mm>Circuit simulation becomes more and more important in integrated circuit design. For VLSI circuits, the simulation usually outputs signal waveforms occupying massive storage space. The compression of these signal waveforms becomes crucial to the efficiency of circuit simulation. Logic simulation mainly outputs the signal values at the time of signal transition and some auxiliary information such as signal name, signal type, signal width. A compression method for auxiliary information is proposed. Then, the signal name compression scheme in existing work is improved according to the characteristics of signal value data, and a more efficient digital waveform compression storage format is proposed. The proposed format is more adaptive to the variable-length coding for compression. At the same time, general compression algorithms can be used for secondary compression, thereby further improve the compression rate. Finally, through parallel computing, the compression and decompression procedure can run in a three-stage pipeline mode. The proposed method largely reduces the compression and decompression time, and can be better integrated within the logic simulator. The experimental results show that with the proposed method the compression rate can be as large as 720. Compared with the existing methods, the compression rate is increased by nearly 23 times with shorter compression and decompression time.

Design and simulation of graphene logic gates using graphene p–n junctions as building blocks

Design and simulation of graphene logic gates using graphene p–n junctions as building blocks

Efficient hardware prototype of ECDSA modules for blockchain applications

This paper concentrates on the hardware implementation of efficient and re- configurable elliptic curve digital signature algorithm (ECDSA) that is suitable for verifying transactions in Blockchain related applications. Despite ECDSA architecture being computationally expensive, the usage of a dedicated stand-alone circuit enables speedy execution of arithmetic operations. The prototype put forth supports N-bit elliptic curve cryptography (ECC) group operations, signature generation and verification over a prime field for any elliptic curve. The research proposes new hardware framework for modular multiplication and modular multiplicative inverse which is adopted for group operations involved in ECDSA. Every hardware design offered are simulated using modelsim register transfer logic (RTL) simulator. Field programmable gate array (FPGA) implementation of var- ious modules within ECDSA circuit is compared with equivalent existing techniques that is both hardware and software based to highlight the superiority of the suggested work. The results showcased prove that the designs implemented are both area and speed efficient with faster execution and less resource utilization while maintaining the same level of security. The suggested ECDSA structure could replace the software equivalent of digital signatures in hardware blockchain to thwart software attacks and to provide better data protection.

Математическое моделирование с неопределенностью в микроэлектронике

The necessity of mathematical modeling with uncertainty for processes and systems in microelectronics is discussed. In such modeling, in fact, evolution of attainable sets of the systems is considered. The cost of such transition to simulation with uncertainty is the increase in mathematics complexity under use. Two examples are considered: etching and deposition simulation; logic simulation for digital circuits.

DETERMINATION OF “WEAK” BY POWER TRANSFORMERS RELIABILITY OF POWER SYSTEMS ACCORDING TO THE RESULTS OF FAILURE RISK ASSESSMENT UNDER EXTERNAL SHORT CIRCUITS

Background. The increase of technological violation intensity and its consequences severity is caused mainly by objectively existing aging and service life depletion of electrical equipment. The power industry liberalization exacerbates the reliable operation problem of the power system and requires identification of power system operation accompanied by the maximum emergency risk with possible cascade accidents development. Therefore, the model development task for assessment of the equipment failure risk based on the diagnostic results of technical condition in particular under short circuit in the external network is relevant today. Objective. The aim of the work is to develop a fuzzy mathematical model for probability assessment of power transformer failure in the presence of a windings defect, short circuit in external network and emergency risk assessment under power transformers out of service. Methods. The fuzzy set theory and fuzzy logic were used for developing a mathematical model of risk assessment of power trans- former failure. The problems of determining the “weak” in terms of power transformers reliability of power systems based on the results of failure risk assessment due to external short circuits were solved by methods of fuzzy logic and probabilistic-statistical simulation of electric power system modes. Results. The necessity of complex simulation of electric power system modes is substantiated for probability assessment of power transformer failure under electrical network disturbances. The simulation of technical condition of power transformer windings was carried out. The short circuit influence on operability level of power transformers of electric power system was investigated. The quantitative indicators of operational risk of electric power system were determined under power transformers out of service. Conclusions. The linguistic mathematical model for estimating the failure probability of power transformer windings in the presence of defect and short circuit in electrical network has been developed to determine the quantitative indicators of emergency risk in power system.

Design and simulation of optical logic gates based on insulator - metal – insulator (IMI) plasmonic waveguides for optical communications

In this study, a structure has been proposed implementing the optical Plasmonic logic gates (OR, NOR, AND, NAND, NOT) using the linear Plasmonic waveguide and the double ring resonator. The results of these gates were analyzed and simulated by means of Comsol Multiphysics (5.6) using Finite Element Analysis (2-FEM). These gates were implemented in the same structure depending on the characteristic of constructive and destructive optical interference between the signals propagating in the input ports and the control port, the phase and direction of those signals, as well as the positions of these ports. Hence, the performance of these gates was measured according to two criteria, first, the optical transmission ratio and the second, the contrast ratio, which is the ratio between the transmitter ON state of logic (1) and OFF for logic (0).

Design and Simulation of Optical Logic Gates Based on (MIM) Plasmonic Waveguides and slot cavity resonator for Optical Communications

In the field of optics the tinier devices are the better; therefore, the diffraction limit of light seems like an essential limitation in the way of that field. In return, new methods have appeared to resolve this issue. One of these methods is the plasmonic technology which allows light pressure into nanostructures. The current study proposes all-optical logic gates based on metal insulator metal structures (mim) waveguide. This waveguide has an important characteristic which is restricting the applied light strongly far from the diffraction limit. The proposed structure is small compared to the applied wavelength. The optical plasmonic gates proposed are (OR, NOR, AND, NAND, NOT). The comsol multiphysics 5.5 software was used for simulation by the 2-D FDTD method. Hence, these five gates will be obtained by optical interference between the propagating signals through the input ports and the control ports, whose positions can be altered according to the gate needed. The implementation and simulation of the proposed gates were all in the same structure, with the same dimensions, the same wavelength and the same transmission threshold, with applicable wavelength of (1550 nm). The performance of the proposed plasmonic gates was tested by two criteria; the optical transmission ratio and the contrast ratio, which is the ratio between the ON and OFF states of the proposed gate..

Fuzzy mamdani logic inference model in the loading of distribution substation transformer SCADA system

&lt;span id="docs-internal-guid-152e332e-7fff-7073-a541-1d420decb47b"&gt;&lt;span&gt;The research objective of supervisory control and data acquisition (SCADA), with fuzzy Mamdani logic simulation on the loading section of distribution transformer substations. Data acquisition is available when saving SAIFI SAIDI data and storing the results of monitoring equipment. The method used is Mamdani fuzzy logic, there are two input variables, namely current and voltage devices. The membership function in Mamdani fuzzy logic has been created based on the input current and voltage variables. Currently: parameter {0, 600} low is created {0, 350, 450, 600}, normal {400-650} parameter is created {400, 500, 550, 650}, parameter high {≥600} is created {600, 650, 750, 1000}, when determining the voltage: low {≤10.5} parameters {0 4 7 10.5}, normal {9-14} parameters {9, 10, 13, 14} and high {≥13} - parameters {13, 14, 15, 16}. Based on the results of the Mamdani logic rule test on the output current containing a transformer and a voltage sensor, the results obtained are IF (normal current; (630) AND voltage (high); (13.2) (high load transformer). The components in the simulation tool include miniature substations made with the 1A travel substation model, 3A substation as the main substation, the relay as distribution substation as the monitoring application. Telestatus and Telecontrol use a microcontroller. Initial scenario. After substation is resumed, data is stored after downtime, service life, duration, and data period. Initial scenario After substation is resumed, data is stored after downtime, service life, duration, and data period.&lt;/span&gt;&lt;/span&gt;

Numerical simulation of all-optical logic gates based on hybrid-cavity semiconductor lasers.

All-optical switch and multiple logic gates have been demonstrated using a hybrid-cavity semiconductor laser composed of a square microcavity and a Fabry-Perot cavity experimentally. In this paper, two-section tri-mode rate equations with optical injection terms are proposed and applied to study all-optical logic gates of NOT, NOR, and NAND operations utilizing the hybrid-cavity laser. Steady-state and dynamical characteristics of all-optical multiple logic gates are simulated, taking into account the influence of mode frequency detuning, gain suppression coefficients, mode Q factor, injection energy, and biasing current. All-optical logic NOT, NOR, and NAND gates up to 20, 15, and 20 Gbit/s are obtained numerically with dynamic extinction ratios of over 20, 20, and 10 dB, respectively, which are potential response speeds of the all-optical logic gates based on the hybrid-cavity semiconductor lasers.