Development of a general purpose First-In-First-Out (FIFO) core

Abstract

First-In-First-Out cores (FIFOs) are memory storage elements that are used in digital systems for buffering data through a system for later processing. This paper presents the design and implementation of a General Purpose FIFO Core which allows adjustment of the capacity along with the size of each data word. Status indicators were provided to indicate whether or not the FIFO was empty, half-full, or full. The number of data words stored in the FIFO was also indicated by designated output ports of the system. A status flag was also available to indicate when the size reached a predetermined threshold value. A separate interface was provided that allowed the data at any address to be accessed for reading. It was also possible to write a data word to the back of the FIFO while another data word was read from the front simultaneously. The FSM-D architectural model was applied to the design of the FIFO Core and the implementation was done in VHDL using the Xilinx ISE 14.7. The implemented core was simulated using ISim Logic Simulator of the Xilinx ISE platform, and it was found that the system core behaved as specified by the test cases.