Design and implementation of IP core for RoadRunneR-128 block cipher

Abstract

RoadRunneR-128 is a recently invented light weight, Feistel-type bit slice block cipher with a block size of 64 bits and key length of 128 bits. RoadRunneR is specifically designed to offer a better performance in resource constrained 8-bit platforms. This cipher is highly optimised for implementation on 8-bit CPUs with proven security against linear and differential attacks. The paper deals with design and hardware implementation of a soft IP core for RoadRunneR-128 on FPGA. The paper then discusses the performance, resource utilization and estimated power consumption of the design on ALTERA DE1 cyclone II FPGA. It is inferred that the implemented design of RoadRunneR-128 is well suited for light weight platforms, and performs at a maximum clock frequency of 272.18 MHz, throughput of 65 Mbps, and an efficiency of 0.081 Mbps/slice. The work presented here, evidently outperforms its previous hardware implementations, since the invention of the cipher in 2015. The implemented cipher is found to be lighter, and the performance and the security are comparable with its competitors like AES, PRIDE and SPECK.