Abstract
In this paper, it introduces the design and implementation of custom IP core for liquid crystal display (LCD) controller based on system on a programmable chip (SOPC) technology and Verilog hardware description language (HDL). The IP core can be put up as a general-purpose peripheral module to the Avalon Bus, communicating with the NIOS II through registers, and the underlying sequential logic for communicating with the external LCD liquid crystal module is automatically completed by the module. The driver does not need to care about the details of the underlying timing, it only needs to implement the read and write operations of the LCD data through register access, thus achieve the purpose of controlling the display content of the LCD. In addition to reducing the complexity of driver development, the design can also take full advantage of the parallel operation of hardware logic to improve the execution efficiency of the entire system and the throughput of processing tasks, especially in some occasions where high-speed image real-time processing is required. Simulations and experiments show that the IP core for LCD controller has good stability, versatility and compatibility.
Highlights
The liquid crystal display (LCD) controller design scheme using a piece of complex programmable logic device (CPLD) and a piece of frame storage is introduced in detail [1]
The field programmable gate array (FPGA) is more flexible in programming than CPLD; the programming method of CPLD is to modify the logic function with fixed internal circuit, and the programming mode of FPGA is mainly to change the wiring of internal connections; CPLD has more advantages on completing various algorithms and combinational logic and FPGA is more suitable for tasks that require higher timing logic; FPGA is more suitable than CPLD for the design of LCD controller with relatively high timing requirements
The advantages and process of system on a programmable chip (SOPC) software and hardware collaborative design are expounded in detail [7]; in addition to reducing the complexity of driver development, hardware and software collaborative design can make full use of the advantages of hardware logic to run in parallel; thereby improving the overall system execution efficiency and processing task throughput, especially in some situations where high-speed image real-time processing is required
Summary
The LCD controller design scheme using a piece of complex programmable logic device (CPLD) and a piece of frame storage is introduced in detail [1]. Due to the properties of open structure, parallel processing design with FPGA is possible and designed [2,3,4] It describes the design and implementation of a multi-function LCD controller based on FPGA, introduces the overall structure of the controller, and describes in detail the design and implementation methods of each module and the pivotal technologies involved [2]. The FPGA-based TFT-LCD controller is designed, the module design using Verilog HDL solves the problem of real-time image display of the embedded system, saves development cost and development time cost, and expands the application range [5]. It is the first complete hardware evolution (CHE) based on SOPC for EH. Made with COB technology, the structure is stable and the service life is long
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