Efficient Digital Waveform Compression Method for Logic Simulation of Integrated Circuits

Abstract

<p indent=0mm>Circuit simulation becomes more and more important in integrated circuit design. For VLSI circuits, the simulation usually outputs signal waveforms occupying massive storage space. The compression of these signal waveforms becomes crucial to the efficiency of circuit simulation. Logic simulation mainly outputs the signal values at the time of signal transition and some auxiliary information such as signal name, signal type, signal width. A compression method for auxiliary information is proposed. Then, the signal name compression scheme in existing work is improved according to the characteristics of signal value data, and a more efficient digital waveform compression storage format is proposed. The proposed format is more adaptive to the variable-length coding for compression. At the same time, general compression algorithms can be used for secondary compression, thereby further improve the compression rate. Finally, through parallel computing, the compression and decompression procedure can run in a three-stage pipeline mode. The proposed method largely reduces the compression and decompression time, and can be better integrated within the logic simulator. The experimental results show that with the proposed method the compression rate can be as large as 720. Compared with the existing methods, the compression rate is increased by nearly 23 times with shorter compression and decompression time.