Gate-oxide-short defect analysis and fault modeling in FinFETs

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FinFET has caused new challenges in reliable device testing due to its three-dimensional structure and reduced critical dimensions. Accurate defect modeling and generation of reliable fault models are essential to create realistic set of test patterns to detect defects. Cell-Aware Test (CAT) has significantly improved the detection of cell-internal defects in MOSFET-based circuits. However, the defect models utilized are obtained based on the defects injected at the layout level and represented by fixed lumped passive components that cannot reflect the true defect nature in the complex 3D structure of FinFET. Gate-oxide-short (GOS) is one of the defects that has significant impact on circuit reliability. This paper focuses on the 3D physical device structure, rather than the layout. The analysis is based on the 3D bulk FinFET template provided by Synopsys. We have performed DC and transient simulations on defective FinFETs with various defect locations and sizes in the Sentaurus TCAD environment. The comprehensive investigation of the GOS defect has led to the development of accurate defect models. These models are applied as Verilog-A modules in circuit-level simulation of complex logic gates such as And-Or-Invert (AOI) and 3:1 Multiplexer (MUX). We have also extracted the HSPICE model parameters for the FinFET template based on the BSIM-CMG local extraction procedure. The proposed fault modeling methodology is compared to the existing CAT-based approach and demonstrated its superiority. Our methodology is not limited to standard library cells, as the defect models are developed at the device 3D structure instead of the layout.