Logic Nonvolatile Memory Research Articles

Nanosheet-Compatible Complementary-Field Effect Transistor Logic Non-Volatile Memory Device

This study proposes a logic non-volatile memory (NVM) device based on the state-of-the-art gate-all-around (GAA) nanosheet process. By adopting a complementary FET structure, we not only reduce the layout footprint area but also demonstrate the compatibility with sub-3nm nanosheet CMOS technology. We simulated the device in TCAD for program and erase operations, considering both Fowler Nordheim tunneling and hot carrier injection mechanisms. The memory window is optimized by adjusting the device structure, such as tunneling and blocking oxide thicknesses, top- and bottom-channel width, and the floating gate length, resulting in a significant enhancement in the memory window. Finally, NAND/NOR type CFET logic NVM are demonstrated to reveal the possible applications of gate-all-around stacked junctionless nanosheet transistor towards embedded flash.

Design and optimization of multiple-time programmable memory cell by advanced CMOS FinFET technologies

This paper presents a new multiple-time programmable (MTP) memory cell that features an n-well as the erasing gate and is implemented in a 16 nm FinFET technology process. It is composed of slot contacts placed beside a metal gate for lateral coupling to the floating gate, while an n-well with a floating gate laid on top of it functions as erasing terminal. With adjusted slot contact length, a programming gate (PG) coupling ratio can be designed for the optimized program, erase and read operations to best meet the needs for logic non-volatile memory array development. An increase in the PG coupling ratio provides an increasing read current and lower leakage current, which brings about an improved read window in a larger array. Good endurance test results and disturb immunity were also demonstrated on these new MPT cells.

Self-Clamping Programming in Narrow-Bridge Floating Gate Cells for Multi-Level Logic Non-Volatile Memory Applications

A new self-converging programming characteristic in a single-poly floating-gate memory cell with full-compatibility to a CMOS logic technology is observed and studied. A uniquely design cell with a narrow-bridging line between two coupling capacitors promotes a localized charging effect at the electron tunneling site, leading to clamping of threshold voltage states. Through this mechanism, the new multi time programmable (MTP) cells exhibit tight threshold voltage distributions for multi-level cells (MLC) operations. Improved cycling reliability and one-shot multi-level programming has been fully demonstrated in this work.

Twin-bit via resistive random access memory in 16 nm FinFET logic technologies

A via resistive random access memory (RRAM) cell fully compatible with the standard CMOS logic process has been successfully demonstrated for high-density logic nonvolatile memory (NVM) modules in advanced FinFET circuits. In this new cell, the transition metal layers are formed on both sides of a via, given two storage bits per via. In addition to its compact cell area (1T + 14 nm × 32 nm), the twin-bit via RRAM cell features a low operation voltage, a large read window, good data retention, and excellent cycling capability. As fine alignments between mask layers become possible, the twin-bit via RRAM cell is expected to be highly scalable in advanced FinFET technology.

Gate contact resistive random access memory in nano scaled FinFET logic technologies

A full logic-compatible embedded gate contact resistive random access memory (GC-RRAM) cell in the CMOS FinFET logic process without extra mask or processing steps has been successfully demonstrated for high-density and low-cost logic nonvolatile memory (NVM) applications. This novel GC-RRAM cell is composed of a transition metal oxide from the gate contact plug and interlayer dielectric (ILD) in the middle, and a gate contact and an n-type epitaxial drain terminal as the top and bottom electrodes, respectively. It features low-voltage operation and reset current, compact cell size, and a stable read window. As a promising embedded NVM solution, the compact one transistor and one resistor (1T1R) cell is highly scalable as the technology node progresses. Excellent data retention and cycling capability have also been demonstrated by the reliability testing results. These superior characteristics make GC-RRAM one of a few viable candidates for logic NVM for future FinFET circuits.

Multilevel Anti-Fuse Cells by Progressive Rupturing of the High-<inline-formula> <tex-math notation="LaTeX">$\kappa $ </tex-math> </inline-formula> Gate Dielectric in FinFET Technologies

A new operation scheme is proposed for achieving multilevel storage in FinFET one-time programmable (OTP) cells by a high- $\kappa $ metal gate CMOS process. The OTP cells are programmed by breaking down the gate dielectric layer, during which the corner effect in the FinFET structure shortens the program time and lowers the program voltages. The after-breakdown resistance in the storage node is found to be well-controlled by the compliance current level set by the select transistor. By using WL voltage control, the multilevel OTP cell with superior data retention and disturb immunity is successfully used in advanced logic nonvolatile memory applications.

Improved Performance of Novel Vertical Assist Operating Select Gate Lateral Coupling Cell for Logic Nonvolatile Memory

In this letter, we report a high-performance logic nonvolatile memory for pure logic processes using novel structure and operations. Even though a select gate lateral coupling (SGLC) cell has the advantages of small cell size, fast programming speed, and over-erase-free features, it has a critical problem of on-cell current degradation during a relatively small number of program/erase (P/E) cycles. By installing an assist gate (AG) on an SGLC cell and employing novel operation methods, the cycling performance improved significantly from 100 times to 10 k times. The initial purpose of using AG was for Fowler–Nordheim erasing operation. However, it is not only used for erasing operation but also for programming to enhance the coupling ratio using the novel vertical assist (VA) operating method. Owing to the novel VA-SGLC cell structure and combined vertical and lateral coupling operations, it shows enhanced programming speed, wider $\text{V}_{T}$ window, and higher endurance than the conventional SGLC cell using the same process. As a result, a program time of 10 $\mu \text{s}$ and 10 k times P/E cycling performance, preserving a $\text{V}_{T}$ window of over 4 V, is achieved without additional processes or increasing the cell size.

Titanium-Oxide-Based Slot Contact RRAM in Nanoscaled FinFET Logic Technologies

In this letter, a new ultrahigh-density memory constructed with a contact resistive random access memory (RRAM) is proposed. This slot contact RRAM (SCRRAM) with transition metal oxide from contact liner layers has been successfully demonstrated by a standard 16-nm FinFET process without extra mask or processing step. The new FinFET RRAM features low-power forming and reset operation, stable Low Resistance State (LRS)/High Resistance State (HRS), and compact cell size. As a logic nonvolatile memory (NVM) solution, SCRRAM exhibits high endurance, stable data retention, read and program disturb immunity, which further support this new 1T1R cell as one of the promising embedded NVM solutions in FinFET CMOS generations.

A high density FinFET one-time programmable cell with new intra-fin cell isolation for advanced system on chip applications

A fully CMOS compatible one-time programmable (OTP) cell with a novel intra-fin cell isolation (IFCI) structure on a FinFET CMOS process has been proposed. The IFCI OTP cell utilizes the field-enhanced dielectric breakdown at fin corners to perform a fast and low-voltage program operation. Moreover, an ultrasmall intra-fin cell-to-cell isolation is firstly introduced to markedly shrink the cell size by eliminating the area-consuming spacing of fin-to-fin isolation. The IFCI FinFET OTP with fast program speed, excellent read disturb immunity, and reliable data retention is a promising solution for logic nonvolatile memory (NVM) technology in advanced CMOS nodes.

On-Chip Recovery Operation for Self-Aligned Nitride Logic Non-Volatile Memory Cells in High-K Metal Gate CMOS Technology

A new on-chip recovery operation is proposed in the self-aligned nitride (SAN) cell. Merged nitride spacer is sandwiched between high-k metal gate stacks in nano-meter CMOS process. The scaled gate length enables the SAN cell be erased by band-to-band hot hole. For multiple-time-programming operation, two effective recovery methods are proposed to recover on/off window after cycling stress. Both ac and dc methods are applied to eliminate deep-trapped charges via electrical self-heating. Experimental data demonstrates dc recovery methods that provide nearly full damage anneal capability and, in turn, effectively extend SAN cell’s endurance level.

Control Plug Lateral Coupling Memory Cell Utilizing Uniform Channel Fowler–Nordheim Operation

In this letter, we propose a control-plug (CP) structure logic nonvolatile memory (LNVM) fabricated by a standard logic CMOS process for mobile applications with low-power-consumption requirement. The operating concept of this cell is based on the use of a lateral capacitance coupling between a bar-type CP and a floating gate. Owing to the unique bar-type CP-coupling method and CP-sharing cell array structure, the novel cell has a coupling ratio of over 94% with the lowest fill factor of 344 as a Fowler-Nordheim (FN)-operated LNVM. Furthermore, because of the high coupling ratio and divided-bias operating method, this cell utilizes a uniform-channel FN tunneling program and erase method using a 3.3 V logic peripheral overdrive tolerable voltage of 5.5 V.

A new 28 nm high-k metal gate CMOS logic one-time programmable memory cell

This work presents a high density high-k metal gate (HKMG) one-time programmable (OTP) cell. Without additional processes and steps, this OTP cell is fully compatible to 28 nm HKMG CMOS process. The OTP cell adopts high-k dielectric breakdown as programming mechanism to obtain more than 105 times of on/off read window. Moreover, it features low power and fast program speed by 4.5 V program voltage in 100 µs. In addition to the ultrasmall cell area of 0.0425 µm2, the superior performance of disturb immunities and data retention further support the new logic OTP cell to be a very promising solution in advanced logic non-volatile memory (NVM) applications.

28-nm 2T High-<formula formulatype="inline"><tex Notation="TeX">$K$</tex></formula> Metal Gate Embedded RRAM With Fully Compatible CMOS Logic Processes

A new two-transistor embedded resistive RAM (RRAM) cell with fully Taiwan Semiconductor Manufacturing Company 28-nm CMOS logic compatible process is reported. The new 28-nm logic compatible RRAM cell consists of two logic standard high- k metal gate (HKMG) CMOS transistors with a composite resistive gate dielectric of TiN/ HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si as a resistive memory storage node. Using one of the transistor gates as a source line in RRAM SET/RESET operation, the resistive memory states can be efficiently read and sensed by selecting the other transistor gate and its corresponding bitline. Therefore, the new 2T embedded RRAM cell has realized a logic nonvolatile memory (NVM) solution with cost effective, and fully compatible with 28-nm HKMG CMOS logic platforms. Besides, through adapting the existing high- K gate dielectric in the RRAM cell, the embedded memory cell does not need any additional deposition of resistive film or extra process steps and it will be very scalable and compatible with the fast progress of CMOS technologies in embedded NVM applications. Furthermore, its low voltage requirement makes this cell conveniently fit in logic intellectual properties and circuits for local data storages or level trimming devices on system-on-chip logic NVM products.

A New 2T Contact Coupling Gate MTP Memory in Fully CMOS Compatible Process

A new fully logic process compatible 2T multitime programmable (MTP) memory cell has been introduced for embedded logic nonvolatile memory (NVM) applications. The cell adopts a novel contact coupling gate structure as an additional control gate for highly efficient operation and high-density memory applications. A new 2T n-channel MTP 2-Kb memory test chip has been also successfully demonstrated on pure 0.18- CMOS logic process without extra masking or process step. Furthermore, the embedded 2T MTP cell performs an efficiently program/erase operation by CHE injection and FN tunnel with highly reliable endurance and retention characteristics.

Nanomagnet Logic from Partially Irradiated Co/Pt Nanomagnets

This paper presents a computational study of logic devices built from single-domain Co/Pt nanomagnets, where magnetic properties of the dots are engineered by an inhomogenous focused ion beam (FIB) irradiation. We develop a micromagnetic model for such Co/Pt dots and show that their reversal behavior and coupling to neighboring dots can be precisely engineered by the dose and spatial distribution of the irradiation. We demonstrate that magnetic logic circuits and nonvolatile memory devices with attractive performance figures can be built from asymmetrically irradiated dots.

A High-Density MTP Cell With Contact Coupling Gates by Pure CMOS Logic Process

In this letter, we propose a new fully logic-process-compatible multitime programmable (MTP) memory cell for high-density logic nonvolatile memory (NVM) applications. A very small logic NVM MTP cell has been demonstrated on pure 0.18-μm CMOS process and logic design rules without extra masking and process steps. The MTP cell can be efficiently programmed and erased with a novel tiny contact coupling structure. Very small cell size, fast programming speed, and superior reliability characteristic make the new contact coupling gate MTP cell be one of the most promising solutions in advanced logic NVM application.

A New Differential P-Channel Logic-Compatible Multiple-Time Programmable (MTP) Memory Cell With Self-Recovery Operation

This letter presents a novel differential p-channel logic-compatible multiple-time programmable (MTP) memory cell. This MTP cell has a pair of floating gates, and performs differential read to increase the on/off window. Additionally, a novel self-recovery operation is implemented to boost the floating gate level, thus avoiding the charge-loss problem due to the thin gate oxide requirement in advance logic nonvolatile memory applications. This differential cell with its self-recovery operation is a very promising MTP solution for gate oxide layer with a 70 A thickness, and can be implemented by 3.3 V I/O in 90 nm and the advanced CMOS logic processes such as 45 nm and beyond.

Source Side Injection Programmed P-Channel Self-Aligned-Nitride One-Time Programming Cell for 90 nm Logic Nonvolatile Memory Applications

This study demonstrates a logic compatible p-channel self-aligned-nitride (SAN) cell for one-time programming (OTP) memory applications. The SAN storage structure is independent of the gate oxide thickness, allowing these cells to be performed in a pure advanced logic process beyond 90 nm. The study also exams the characteristics of the source-side injection hot electron (SSIHE) scheme using the simulation tools, and successfully verified the programming characteristics of the p-channel SAN cell with different program voltages. Moreover, this study shows the proposed SAN cell has a wide read current window, high reliability, and superior immunity to disturbance. Combined with a source-side injection scheme, this cell provides a promising solution for advanced logic nonvolatile memory (NVM) applications.

Multilevel Antifuse Cells with Programmable Contact in Pure 90 nm Logic Process

A multilevel oxide antifuse cell with programmable contact, fully compatible with a standard complementary metal–oxide–semiconductor (CMOS) logic process, is firstly presented for logic nonvolatile memory applications. A four-state antifuse cell has a stable read window and a very small cell size of 0.097 µm2/bit. By adopting the multiple stages in oxide breakdown, four states of read current level have been successfully demonstrated on this cell fabricated by a standard 90 nm CMOS logic process. A fast programming speed of 10 µs can be obtained using a low programming voltage of less than 4 V. With excellent technology scalability and adaptability, this multilevel antifuse cell provides a very promising solution for programmable logic beyond a 90 nm technology node.

A Study of Self-Aligned Nitride Erasable OTP Cell by 45-nm CMOS Fully Compatible Process

This brief proposes a new 45-nm erasable one-time programming cell with a self-aligned nitride (SAN) storage node for logic nonvolatile memory (NVM) applications. The CMOS fully logic-compatible cell was successfully demonstrated using 45-nm CMOS technology with a very small cell size of 0.1188 mum2. This cell-adapting source-side-injection programming scheme has a wide on/off window and superior program efficiency. The SAN cell with five terminals for various operational conditions uses an asymmetrical read voltage to verify the position of the stored charge. This cell also exhibits excellent data retention capability even when the thickness of the logic gate oxide is less than 20 A, and the gate length is shorter than 40 nm. This new cell provides a promising solution for logic NVM beyond a 90-nm node.