Improved Performance of Novel Vertical Assist Operating Select Gate Lateral Coupling Cell for Logic Nonvolatile Memory

Abstract

In this letter, we report a high-performance logic nonvolatile memory for pure logic processes using novel structure and operations. Even though a select gate lateral coupling (SGLC) cell has the advantages of small cell size, fast programming speed, and over-erase-free features, it has a critical problem of on-cell current degradation during a relatively small number of program/erase (P/E) cycles. By installing an assist gate (AG) on an SGLC cell and employing novel operation methods, the cycling performance improved significantly from 100 times to 10 k times. The initial purpose of using AG was for Fowler–Nordheim erasing operation. However, it is not only used for erasing operation but also for programming to enhance the coupling ratio using the novel vertical assist (VA) operating method. Owing to the novel VA-SGLC cell structure and combined vertical and lateral coupling operations, it shows enhanced programming speed, wider $\text{V}_{T}$ window, and higher endurance than the conventional SGLC cell using the same process. As a result, a program time of 10 $\mu \text{s}$ and 10 k times P/E cycling performance, preserving a $\text{V}_{T}$ window of over 4 V, is achieved without additional processes or increasing the cell size.