Logic Family Research Articles

High-performance LFSR circuit design based on XOR gates

The research discussed in this article is focused on analysing the effects of XOR gates based on different logic families, namely MOS Current Mode Logic (MCML), dynamic current logic, and PTL, on the performance of linear feedback shift register (LFSR) circuits. The aim of the study is to evaluate the power dissipation and critical path latency of the circuits while comparing the results with earlier works in the field. To achieve this, the researchers implemented the 3, 4, and 5-bit LFSR circuits using Verilog HDL code and synthesized them on the Cadence tool using 90nm CMOS technology. The study concludes that LFSR circuits based on XOR gates outperform previous LFSR circuits in terms of power dissipation. The research also offers a comparative analysis of the different types of XOR gates used in the LFSR circuits, highlighting the advantages and disadvantages of each type. The results of the study can be useful for researchers working in the field of circuit design, as well as for practitioners who are interested in developing low-power and efficient LFSR circuits.

Polyhedral semantics and the tractable approximation of Łukasiewicz infinitely-valued logic

Abstract In this work, we present polyhedral semantics as a means to tractably approximate Łukasiewicz infinitely-valued logic (Ł$_{\infty}$). As Ł$_{\infty}$ is an expressive multivalued propositional logic whose decision problem is NP-complete, we show how to to obtain an approximation for this problem providing a family of multivalued logics over the same language as Ł$_{\infty}$. Each element of the family is associated to a polynomial-time linear program, thus providing a tractable way of deciding each intermediate step. We also investigate properties of the logic system derived from polyhedral semantics and the details of an algorithm for the approximation process.

Semantical investigations on non-classical logics with recovery operators: negation

Abstract We investigate mathematical structures that provide natural semantics for families of (quantified) non-classical logics featuring special unary connectives, known as recovery operators, that allow us to ‘recover’ the properties of classical logic in a controlled manner. These structures are known as topological Boolean algebras, which are Boolean algebras extended with additional operations subject to specific conditions of a topological nature. In this study, we focus on the paradigmatic case of negation. We demonstrate how these algebras are well-suited to provide a semantics for some families of paraconsistent Logics of Formal Inconsistency and paracomplete Logics of Formal Undeterminedness. These logics feature recovery operators used to earmark propositions that behave ‘classically’ when interacting with non-classical negations. Unlike traditional semantical investigations, which are carried out in natural language (extended with mathematical shorthand), our formal meta-language is a system of higher-order logic (HOL) for which automated reasoning tools exist. In our approach, topological Boolean algebras are encoded as algebras of sets via their Stone-type representation. We use our higher-order meta-logic to define and interrelate several transformations on unary set operations, which naturally give rise to a topological cube of opposition. Additionally, our approach enables a uniform characterization of propositional, first-order and higher-order quantification, including restrictions to constant and varying domains. With this work, we aim to make a case for the utilization of automated theorem proving technology for conducting computer-supported research in non-classical logics. All the results presented in this paper have been formally verified, and in many cases obtained, using the Isabelle/HOL proof assistant.

SFQ/DQFP Interface Circuits

The increasing complexity of hybrid superconductive computing systems has made interface circuits between logic families an issue of growing importance. In this paper, interface circuits between single flux quantum (SFQ) and directly coupled quantum flux parametron (DQFP) logic families to achieve high speed, low power hybrid superconductive computing systems are presented. In the proposed DQFP-to-SFQ interface, margins greater than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\pm$</tex-math></inline-formula> 20% for the critical current of the JJs, bias currents, and inductances are exhibited. The margins of the excitation current of the DQFP buffer are -38% and +35% with the frequency of the excitation current in the range of 2 GHz to 10 GHz. In the proposed SFQ-to-DQFP interface, the margins are greater than -33% and +25%. The margins of the excitation current of the DQFP buffer are -50% and +20% for frequencies ranging from 2 GHz to 10 GHz. Since no transformers are required, the physical area of the adiabatic portion of the interface circuits is significantly less than existing interface circuits. The SFQ-to-DQFP interface circuit operates at frequencies approaching 20 GHz. These interface circuits therefore exhibit high parameter margins and operating frequencies while requiring significantly less area as compared to existing interface circuits. The proposed interface circuits support the use of both ultra-low power and high speed logic families in complex hybrid superconductive systems.

Adopting a Standard Track Routing Architecture for Next-Generation Hybrid AC/DC-Biased Logic Circuits

The adiabatic quantum-flux-parametron (AQFP) and rapid single flux quantum (RSFQ) logic families both provide distinct advantages for data processing using superconductor electronics. The development of next-generation AQFP-RSFQ hybrid logic circuits provides the opportunity to combine the benefits of both of these logic families. Adopting a standard track routing architecture for both AQFP and RSFQ layouts provides a unified framework for physical layout synthesis. We demonstrate a standard track routing architecture developed under the ColdFlux project and its implementation within AQFP. An additional advantage of the standard track routing architecture is that it provides a systematic way to overcome metal density requirements for modern-day fabrication processes. It also provides a methodical approach towards strategic moat placement for protection against unwanted flux trapping. Implementations of passive transmission line (PTL) connections and their physical placement for hybrid AQFP-RSFQ circuits are discussed. Several AQFP layouts for the ColdFlux project are redesigned to adopt the standard track routing architecture. Experimental simulation of moat performance is also presented.

A Full-Custom Design Flow and a Top-Down RTL-to-GDS Flow for Adiabatic Quantum-Flux-Parametron Logic Using a Commercial EDA Design Suite

The adiabatic quantum-flux-parametron (AQFP) circuit is a superconductor digital logic family with extremely low power consumption. It consumes five orders less power than the state-of-the-art CMOS circuits and three orders of magnitude less power than RSFQ circuits, another competing digital superconductor technology. The computing resources required by society are increasing every year, and the AQFP circuit is a strong candidate for the next generation of computers. In previous research, a 4-bit MANA microprocessor and a 16-bit Kogge-Stone adder using AQFP logic were designed and demonstrated. These circuits were designed almost by hand, and the development environment needs to be improved to implement AQFP circuits for practical applications. So, we used Synopsys EDA tools typically used for CMOS design to create a full-custom design flow for logic cell design and a top-down flow to design combinational logic circuits automatically. We integrated a circuit design editor with simulation and verification tools for the full-custom design flow. For the top-down flow, we created an environment that automatically performs logic synthesis, path balancing, cell placement, and signal and excitation routing. 1024-bit adders with more than two million Josephson junctions (JJs) have been successfully designed.

All-JJ Logic Based on Bistable JJs

The all-JJ logic family is a promising area and power efficient, scalable single flux quantum (SFQ) technology for application to exascale supercomputers. All-JJ superconductive logic is based on a superconductor-ferromagnet-superconductor (SFS) bistable JJ, enabling nanometer feature sizes in VLSI complexity superconductive systems. In this paper, a mechanical analogy is proposed to describe the dynamic behavior of these bistable JJs. Novel all-JJ logic gates, such as TFF, DFF, OR, AND, and NOT gates, are presented here. All-JJ circuits are composed of bistable JJs, standard JJs, and bias currents, requiring no large inductors within the storage loops. All-JJ logic cells exhibit less delay and power than standard SFQ cells with the same critical current density. All-JJ systems can operate at high frequencies due to the small capacitance of the SFS JJ. A complex all-JJ circuit from the suite of ISCAS'85 benchmark circuits is also characterized. This complex all-JJ circuit exhibits less delay and power as compared to standard SFQ logic. The bias current in a conventional benchmark circuit and all-JJ benchmark circuit is, respectively, 22 mA and 13 mA. The delay of each cell within the conventional benchmark circuit and all-JJ benchmark circuit is, respectively, approximately 20 and 8 ps. A parasitic inductance in series with the JJs disturbs the current distribution within the all-JJ circuits while degrading the margins. To suppress the effects of this parasitic inductance on SFS JJs, small linear inductors are added to manage the current distribution and improve parameter margins.

Two Circuits for Directing and Controlling Ballistic Fluxons

Reversible logic schemes using flux solitons (fluxons) on long Josephson junctions (LJJs) have recently been proposed. The attraction of the fluxon is that it propagates ballistically along an LJJ until it encounters a change in the character of the LJJ, often a designed circuit element. Logic gates involve fluxons interacting with circuit elements and with other fluxons. However, testing of ballistic fluxon circuits requires other circuits outside the logic family to direct and control fluxon motion. We discuss two such <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">non-reversible</i> fluxon control circuits. First, the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">polarity filter gate</i> is a simple non-reversible gate that allows one polarity of fluxon to pass, while reflecting the other polarity. In the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</i> state both polarities reflect. Second, the polarity separator generalizes on the polarity filter concept and allows separation of the two fluxon polarities into different LJJs. We discuss simulations of these structures and possible applications.

An Adiabatic Quantum-Flux-Parametron 8-bit Ripple Carry Adder Using Delay-Line Clocking

Adiabatic quantum-flux-parametron (AQFP) logic is a superconductor logic family that can operate with low switching energy due to adiabatic switching. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, in which the latency for each logic operation is determined by the propagation delay of the excitation current. We demonstrated several AQFP logic gates with delay-line clocking and demonstrated a phase skipping operation, in which some of the AQFP buffers for phase synchronization are removed to reduce the junction count and energy dissipation. In the present study, we design and demonstrate an AQFP 8-bit ripple carry adder with delay-line clocking to show that delay-line clocking and the phase skipping operation are applicable to large-scale AQFP circuits. The latency of this adder is 960 ps, which is 40% of that for a conventional design. Moreover, due to the phase skipping operation, the junction count is reduced to approximately 70% of that for the conventional design. We find that this adder can operate at up to 4 GHz. The above results indicate that large-scale AQFP circuits can operate with low latency and low junction count by using delay-line clocking and a phase skipping operation.

Optimization and Verification of RSFQ and AQFP Logic Circuits Using JoSIM Tools

Various techniques exist to optimize functioning RSFQ circuits for improved critical margins. Existing techniques generally employ a center of gravity method. We present the additional use of a minimal distance to failure optimization technique through the ad-hoc tools for the superconducting circuit simulation engine JoSIM. These techniques are used to optimize the margins of RSFQ circuits through verification of Josephson junction phase. This verification method is extended to incorporate the output current in an attempt to optimize the highly energy efficient AQFP logic family. Results are presented for pre and post optimized logic circuits for both families.

Power Optimization of 50 GHz ERSFQ Circuits

The Energy-efficient Rapid Single Flux Quantum (ERSFQ) logic family offers zero-static power dissipation. Any ERSFQ circuit requires a feeding Josephson transmission line (FJTL), a relatively large active transmission line, which serves as an accurate voltage source. For proper operation, the FJTL needs to be continuously pumped at a frequency that is equal to or higher than the highest clock frequency of the ERSFQ circuit. We selected an on-chip pseudo-random binary sequence (PRBS) generator as the example circuit since it naturally facilitates quantitative measurements of operating bias margins in terms of bit error rate (BER). Using external and internal flux pump sources, we performed extensive experimental studies on BER for ERSFQ PRBS generators operating at clock frequencies up to 50 GHz. We paid special attention to the over-pumping regime, where the FJTL pump frequency is higher than the PRBS clock frequency and confirmed its superiority in improving BER. At 35.56 GHz clock frequency, a group of 4 PRBS generators and 4 individual FJTLs with the bias current ratio (BCR) equal to 1, had a BER lower than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> and bias margins of ±25% for internal and external flux pump sources over-pumping at 6.25% above clock frequency. The maximal operational clock frequency of a single ERSFQ PRBS generator with intrinsic pump source (+6.25% over-pumping) and BER <10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> was 49.53 GHz. We also focused on optimization of the FJTL's size to reduce the power consumption and the area occupied by the FJTL itself. All chips were fabricated at MIT-Lincoln Laboratory using the SFQ5ee fab node. Future steps required for better understanding of ERSFQ operation are discussed.

Model-Checking for Ability-Based Logics with Constrained Plans

We investigate the complexity of the model-checking problem for a family of modal logics capturing the notion of “knowing how”. We consider the most standard ability-based knowing how logic, for which we show that model-checking is PSpace-complete. By contrast, a multi-agent variant based on an uncertainty relation between plans in which uncertainty is encoded by a regular language, is shown to admit a PTime model-checking problem. We extend with budgets the above-mentioned ability-logics, as done for ATL-like logics. We show that for the former logic enriched with budgets, the complexity increases to at least ExpSpace-hardness, whereas for the latter, the PTime bound is preserved. Other variant logics are discussed along the paper.

Sigmoid function generator using stochastic adiabatic superconductor logic

Stochastic-computing-based artificial neural networks (SC-ANNs) can be used to perform hardware- and energy-efficient neuromorphic computing. We have been developing SC-ANNs using an energy-efficient superconductor logic family, namely, adiabatic quantum-flux-parametron (AQFP) logic. AQFP logic is suitable as a building block for SC-ANNs since it can perform stochastic operations with extremely small energy dissipation. In this Letter, we propose and demonstrate a sigmoid function generator (SFG) for AQFP SC-ANNs, which we refer to as the AQFP SFG. An SFG is an important circuit in neural networks that generates outputs from the sum of weighted inputs in accordance with the sigmoid function. The AQFP SFG performs the sigmoid function using a finite state machine based on an AQFP buffer coupled to a flux storage loop. We experimentally demonstrate that the AQFP SFG generates output signals from stochastic bitstreams in accordance with the sigmoid function and that the characteristics of the sigmoid function can be controlled by a bias current. Furthermore, we show that the AQFP SFG operates with small power dissipation due to its simple structure.

Nontraditional Design of Dynamic Logics Using FDSOI for Ultra-Efficient Computing

In this paper, we propose a non-traditional design of dynamic logic circuits using Fully-Depleted Silicon on Insulator (FDSOI) FETs. FDSOI FET allows the threshold voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_t</i> ) to be adjustable (i.e., low-Vt and high-Vt states) by using the back gate bias. Our design utilizes the front and back gates of an FDSOI FET as the input terminals and proposes the dynamic logic gates (like; NAND, NOR, AND, OR, XOR, and XNOR) and circuits (like; half adder and full adder). It requires fewer transistors to build dynamic logic gates and achieves high performance with low power dissipation compared to conventional dynamic logic designs. The compact industrial model of FDSOI FET (BSIM-IMG) has been used to simulate dynamic logic gates and is fully calibrated to reproduce the 14nm FDSOI FET technology node data. Calibration is performed for both electrical characteristics and process variations. The simulation results show an average improvement in transistor count, propagation delay, power, and power-delay product of 23.43%, 57.16%, 47.05%, and 77.29%, respectively, compared to the conventional designs. Further, our design reduces the charge sharing effect, which affects the drivability of the dynamic logic gates. In addition, we have analyzed the impact of the process, supply voltage, and load capacitance variations on the propagation delay of the dynamic logic family in detail. The results show that these variations have a minor impact on the propagation delay of the proposed FDSOI-based dynamic logic gates compared to the conventional dynamic logic gates.

Cubic Paraconsistent Analysers with Evidence Filter and Temporal Analysis

Ambiguous or inconsistent information is frequently present in the input of any real-world system that relies on multiple data sources. In the presence of inconsistencies, an expert system based on classical logic is trivialised due to the principle of explosion, that forces any proposition (and its negation) to be inferred. Instead, a family of non-classical logics, called Paraconsistent Logics, formalises the idea that even from inconsistent premises, useful conclusions can be drawn. Within this context, the Paraconsistent Annotated Logics with Annotation of Two Values (PAL2v), which use a pair of favourable and unfavourable evidences as annotations, have been particularly successful in engineering applications. Structures called Para-Analysers can be built with these logics that provide the appropriate means to analyse the truth value of a proposition under conflicting/contradictory evidences. The work reported in this paper extends the traditional Para-Analysers with an evidence filter. This new model can be represented as a cubic structure representing various Para-Analyser lattices, each of which is selected according to the quality of the evidence, that is updated with respect to measurements executed at run time. The resulting three-dimensional paraconsistent analysis structure is encapsulated as an expert-system cell called Cubic Paraconsistent Analyser with Evidence Filter and Temporal Analysis (CPAet). Sets of CPAet nodes are combined constituting distinct network topologies that are used to infer the operating conditions of equipment in data networks of electrical systems control and supervision, resulting in a fault detection and classification system. Tests on simulated systems show that the CPAet networks were effective to deal with inconsistencies without trivialising the inferences, while also providing a more informed (finer grained) decision on the data network equipment state, when compared to the traditional paraconsistent analysers.

Active loaded source-coupled logic: Applications and performance comparison

In this paper, we provide an extensive analysis of the newly introduced Active Loaded Source-Coupled Logic (ALSCL) family, which is a single-ended type of logic gate family with source-coupled circuit working principles. The proposed source-coupled logic family has analog-friendly behavior similar to previous source-coupled logic circuits, however, the proposed circuit structure has a simpler design methodology with high noise margins and robust characteristics to the device sizing, process variations, and temperature. Circuit design principles of the proposed ALSCL circuits are described, and performance analysis of various implementations is evaluated. The proposed logic circuit structure performance is tested using 0.18 µm technology with extensive simulations. The proposed logic family has simpler routing requirements compared to classical source-coupled circuits. The proposed circuit structure is functional without fine adjustment of the device sizing and the performance can be tuned by the bias current of the circuits, providing a wide range of performance characteristics with the trade-off for power consumption.

Principles of Logic Design with Nanoscale Thin Film Memristive Systems for High Performance Digital Circuit Applications

The characteristic pinched hysteresis behavior of memristors has been reported by stacks of a variety of materials. This paper aims to examine the principles of logic design using such two terminal memristive systems for high performance digital circuit applications. As against logic design with standard CMOS, the benefits of logic design with memristors have been stated. The realization and operation of memristor based AND and OR hybrid logic gates obtained by integrating memristors with standard CMOS logic have been discussed. The IMPLY and MAGIC logic families have been demonstrated by covering MAGIC NOR and NAND logic gate implementation with MAGIC NOR in detail. A qualitative comparison has been drawn towards the end of the paper to conclude on the suitability and application space for each of the logic families studied in this paper. This work also describes the hybrid CMOS-memristive logic family known as MRL (Memristor Ratioed Logic). With the addition of CMOS inverters, this logic family's OR and AND logic gates, which are based on memristive components, are given a full logic structure and signal restoration. The MRL family, in contrast to earlier memristor-based logic families, is compatible with conventional CMOS logic.

A nanocryotron memory and logic family

The development of superconducting electronics based on nanocryotrons has been limited so far to few device circuits, in part due to the lack of standard and robust logic cells. Here, we introduce and experimentally demonstrate designs for a set of nanocryotron-based building blocks that can be configured and combined to implement memory and logic functions. The devices were fabricated by patterning a single superconducting layer of niobium nitride and measured in liquid helium on a wide range of operating points. The tests show 10 − 4 bit error rates with above ± 20 % margins up to 50 MHz and the possibility of operating under the effect of an out-of-plane 36 mT magnetic field, with ± 30 % margins at 10 MHz. Additionally, we designed and measured an equivalent delay-flip-flop made of two memory cells to show the possibility of combining multiple building blocks to make larger circuits. These blocks may constitute a solid foundation for the development of nanocryotron logic circuits and finite-state machines with potential applications in the integrated processing and control of superconducting nanowire single-photon detectors.

A low power design using FinFET based adiabatic switching principle: Application to 16-Bit arithmetic logic unit

This paper presents a novel 16-bit arithmetic logic unit (ALU) design by cascading simple 1-bit ALUs using metal–oxide-semiconductor field effect transistor (MOSFET) and FinFET technologies while incorporating adiabatic switching principle. Analyses are carried out at 32 nm Berkley predictive technology module (PTM). The paper has employed popular standard adiabatic logic families– such as quasi-static energy recovery logic (QSERL), two phase drive adiabatic dynamic complementary metal oxide semiconductor (CMOS) logic (2PADCL), adiabatic dynamic CMOS logic (ADCL), and two phase clocked adiabatic static CMOS logic (2PASCL). Single-phase adiabatic logic circuit is also introduced. Results show that the proposed technique has power savings of 67.14 %, 39.47 %, 34.65 %, 8.73 %, and 4.16 % for CMOS, QSERL, 2PADCL, ADCL, and 2PASCL respectively with MOSFET technology whereas, it saves 95.22 %, 21.34 %, 20.75 %, 15.66 %, and 8.69 % respectively for same literatures with FinFET technology.

Simplification logic for the management of unknown information

This paper aims to contribute to the extension of classical Formal Concept Analysis (FCA), allowing the management of unknown information. In a preliminary paper, we define a new kind of attribute implications to represent the knowledge from the information currently available. The whole FCA framework has to be appropriately extended to manage unknown information. This paper introduces a new logic for reasoning with this kind of implications, which belongs to the family of logics with an underlying Simplification paradigm. Specifically, we introduce a new algebra, named weak dual Heyting Algebra, that allows us to extend the Simplification logic for these new implications. To provide a solid framework, we also prove its soundness and completeness and show the advantages of the Simplification paradigm. Finally, to allow further use of this extension of FCA in applications, an algorithm for automated reasoning, which is directly built from logic, is defined.