SFQ/DQFP Interface Circuits

Abstract

The increasing complexity of hybrid superconductive computing systems has made interface circuits between logic families an issue of growing importance. In this paper, interface circuits between single flux quantum (SFQ) and directly coupled quantum flux parametron (DQFP) logic families to achieve high speed, low power hybrid superconductive computing systems are presented. In the proposed DQFP-to-SFQ interface, margins greater than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\pm$</tex-math></inline-formula> 20% for the critical current of the JJs, bias currents, and inductances are exhibited. The margins of the excitation current of the DQFP buffer are -38% and +35% with the frequency of the excitation current in the range of 2 GHz to 10 GHz. In the proposed SFQ-to-DQFP interface, the margins are greater than -33% and +25%. The margins of the excitation current of the DQFP buffer are -50% and +20% for frequencies ranging from 2 GHz to 10 GHz. Since no transformers are required, the physical area of the adiabatic portion of the interface circuits is significantly less than existing interface circuits. The SFQ-to-DQFP interface circuit operates at frequencies approaching 20 GHz. These interface circuits therefore exhibit high parameter margins and operating frequencies while requiring significantly less area as compared to existing interface circuits. The proposed interface circuits support the use of both ultra-low power and high speed logic families in complex hybrid superconductive systems.