Logic Family Research Articles

The Dynastic Imagination: Family and Modernity in Nineteenth-Century Germany

The Dynastic Imagination: Family and Modernity in Nineteenth-Century Germany

Neutral Free Logic: Motivation, Proof Theory and Models

Free logics are a family of first-order logics which came about as a result of examining the existence assumptions of classical logic (Hintikka The Journal of Philosophy, 56, 125–137 1959; Lambert Notre Dame Journal of Formal Logic, 8, 133–144 1967, 1997, 2001). What those assumptions are varies, but the central ones are that (i) the domain of interpretation is not empty, (ii) every name denotes exactly one object in the domain and (iii) the quantifiers have existential import. Free logics reject the claim that names need to denote in (ii). Positive free logic concedes that some atomic formulas containing non-denoting names (including self-identity) are true, negative free logic treats them as uniformly false, and neutral free logic as taking a third value. There has been a renewed interest in analyzing proof theory of free logic in recent years, based on intuitionistic logic in Maffezioli and Orlandelli (Bulletin of the Section of Logic, 48(2), 137–158 2019) as well as classical logic in Pavlović and Gratzl (Journal of Philosophical Logic, 50, 117–148 2021), there for the positive and negative variants. While the latter streamlines the presentation of free logics and offers a more unified approach to the variants under consideration, it does not cover neutral free logic, since there is some lack of both clear formal intuitions on the semantic status of formulas with empty names, as well as a satisfying account of the conditional in this context. We discuss extending the results to this third major variant of free logics. We present a series of G3 sequent calculi adapted from Fjellstad (Studia Logica, 105(1), 93–119 2017, Journal of Applied Non-Classical Logics, 30(3), 272–289 2020), which possess all the desired structural properties of a good proof system, including admissibility of contraction and all versions of the cut rule. At the same time, we maintain the unified approach to free logics and moreover argue that greater clarity of intuitions is achieved once neutral free logic is conceptualized as consisting of two sub-varieties.

Comparison of Power Efficient Inverter Circuit using adiabatic technique

The power decadence in conventional CMOS (Complementary Metal oxide Semiconductor) circuit can be diminished by utilizing adiabatic method. Working of Adiabatic logic depends on switching activities, which diminishes the power by giving energy dissipated as heat back to supply. Adiabatic word has come from thermodynamic framework which says that no heat transfer take place from framework to climate as well as the other way around. Adiabatic logic is well known as energy recovery logic because its main objective is to reuse energy. It reuses the energy back to the power supply along the lines diminishing the power dissipation. Adiabatic procedures depend on adiabatic logic guideline. Anu Priya has propose the technique in 2014 [3], of adiabatic procedure where energy dissipation in PMOS organization can be limited and some of energy dissipated at load capacitance can be reused rather than dispersed as heat. Yet, the adiabatic method is exceptionally reliant upon parameter variation. Expecting completely adiabatic activity from a circuit is practically not possible as it is an ideal condition, also adiabatic technology is highly dependent on parameter variations so it’s quite difficult to achieve and ideal adiabatic circuit. It could be just accomplished with extremely sluggish exchanging speed. In examination, three logic families, ECRL (Efficient Charge Recovery Logic), PFAL (Positive Feedback Adiabatic Logic) and CPAL (Complementary Pass Transistor Adiabatic Logic) are contrasted and conventional CMOS logic for inverter circuit. MICROWIND technology is used while investigating different adiabatic circuits; energy utilization is broke down by variety of parameter. Result shows that adiabatic strategy is better decision in case of underpowered application in explicit frequency range.

Optimizing the computation of overriding in [formula omitted

One of the factors that is hindering the adoption of nonmonotonic description logics in applications is performance. Even when monotonic and nonmonotonic inferences have the same asymptotic complexity, the implementation of nonmonotonic reasoning may be significantly slower. This happens also with the family of nonmonotonic logics DLN.In this work we address this issue by introducing two optimizations for reasoning in DLN. The first optimization, called optimistic evaluation, aims at exploiting incremental reasoning in a better way. The second is a module extractor forDLN, that has the purpose of focusing reasoning on a relevant subset of the knowledge base. The proposed optimization iterates the module extractor that, unlike classical module extractors, is not idempotent, in general.We prove that the proposed optimizations are correct and complete, and assess them through extensive experiments. Our results prove that optimized DLN reasoning is often compatible with interactive query answering, which brings nonmonotonic description logics closer to practical applications.

Finite Entailment of Local Queries in the Z Family of Description Logics

In the last few years the field of logic-based knowledge representation took a lot of inspiration from database theory. A vital example is that the finite model semantics in description logics (DLs) is reconsidered as a desirable alternative to the classical one and that query entailment has replaced knowledge-base satisfiability (KBSat) checking as the key inference problem. However, despite the considerable effort, the overall picture concerning finite query answering in DLs is still incomplete. In this work we study the complexity of finite entailment of local queries (conjunctive queries and positive boolean combinations thereof) in the Z family of DLs, one of the most powerful KR formalisms, lying on the verge of decidability. Our main result is that the DLs ZOQ and ZOI are finitely controllable, i.e. that their finite and unrestricted entailment problems for local queries coincide. This allows us to reuse recently established upper bounds on querying these logics under the classical semantics. While we will not solve finite query entailment for the third main logic in the Z family, ZIQ, we provide a generic reduction from the finite entail- ment problem to the finite KBSat problem, working for ZIQ and some of its sublogics. Our proofs unify and solidify previously established results on finite satisfiability and finite query entailment for many known DLs.

Adapting the RACER Architecture to Integrate Improved In-ReRAM Logic Primitives

Modern computing applications based upon machine learning can incur significant data movement overheads in state-of-the-art computers. Resistive-memory-based <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">processing-using-memory</i> (PUM) can mitigate this data movement by instead performing computation <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in situ</i> (i.e., directly within memory cells), but device-level limitations restrict the practicality and/or performance of many PUM architecture proposals. The RACER architecture overcomes these limitations, by proposing efficient peripheral circuitry and the concept of bit-pipelining to enable high-performance, high-efficiency computation using small memory tiles. In this work, we extend RACER to adapt easily to different PUM logic families, by (1) modifying the device access circuitry to support a wide range of logic families, (2) evaluating three logic families proposed by prior work, and (3) proposing and evaluating a new logic family called OSCAR that significantly relaxes the switching voltage constraints required to perform logic with resistive memory devices. We show that the modified RACER architecture, using the OSCAR logic family, can enable practical PUM on real ReRAM devices while improving performance and energy savings by 30% and 37%, respectively, over the original RACER work.

Design of Discrete Hopfield Neural Network Using a Single Flux Quantum Circuit

AbstractThe superconductor single flux quantum (SFQ) logic family has been recognized as a promising candidate to resolve the energy consumption crisis in the post-Moore era, owing to its high switching speed and low power consumption. In the field of machine learning, where technology and computational require-ments are growing rapidly (e.g., image recognition and natural language processing), there is great potential for the implementa-tion of SFQ circuits. In this study, we investigate and implement a discrete Hopfield neural network (DHNN) using SFQ circuits. A DHNN is a binary neural network with less information than a standard full precision neural network; it also provides a higher processing speed. It is mainly used for pattern recognition and recovery. We designed the DHNN circuit with two patterns, each with eight elements. The circuit operates at the clock frequency of more than 50 GHz.

A 16-Bit Parallel Prefix Carry Look-Ahead Kogge-Stone Adder Implemented in Adiabatic Quantum-Flux-Parametron Logic

Extremely energy-efficient logic devices are required for future low-power high-performance computing systems. Superconductor electronic technology has a number of energy-efficient logic families. Among them is the adiabatic quantum-flux-parametron (AQFP) logic family, which adiabatically switches the quantum-flux-parametron (QFP) circuit when it is excited by an AC power-clock. When compared to state-of-the-art CMOS technology, AQFP logic circuits have the advantage of relatively fast clock rates (5 GHz to 10 GHz) and 5 - 6 orders of magnitude reduction in energy before cooling overhead. We have been developing extremely energy-efficient computing processor components using the AQFP. The adder is the most basic computational unit and is important in the development of a processor. In this work, we designed and measured a 16-bit parallel prefix carry look-ahead Kogge-Stone adder (KSA). We fabricated the circuit using the AIST 10 kA/cm2 High-speed STandard Process (HSTP). Due to a malfunction in the measurement system, we were not able to confirm the complete operation of the circuit at the low frequency of 100 kHz in liquid He, but we confirmed that the outputs that we did observe are correct for two types of tests: (1) critical tests and (2) 110 random input tests in total. The operation margin of the circuit is wide, and we did not observe any calculation errors during measurement.

Non-Deterministic Matrices: Theory and Applications to Algebraic Semantics

AbstractWe call multioperation any operation that return for even argument a set of values instead of a single value. Through multioperations we can define an algebraic structure equipped with at least one multioperation. This kind of structure is called multialgebra. The study of them began in 1934 with the publication of a paper of Marty. In the realm of Logic, multialgebras were considered by Avron and his collaborators under the name of non-deterministic matrices (or Nmatrices) and used as semantics tool for characterizing some logics which cannot be characterized by a single finite matrix. Carnielli and Coniglio introduced the semantics of swap structures for LFIs (Logics of Formal Inconsistency), which are Nmatrices defined over triples in a Boolean algebra, generalizing Avron’s semantics. In this thesis, we will introduce a new method of algebraization of logics based on multialgebras and swap structures that is similar to classical algebraization method of Lindenbaum-Tarski, but more extensive because it can be applied to systems such that some operators are non-congruential. In particular, this method will be applied to a family of non-normal modal logics and to some LFIs that are not algebraizable by the very general techniques introduced by Blok and Pigozzi. We also will obtain representation theorems for some LFIs and we will prove that, within out approach, the classes of swap structures for some axiomatic extensions of mbC are a subclass of the class of swap structures for the logic mbC.Abstract prepared by Ana Claudia de Jesus Golzio.E-mail: anaclaudiagolzio@yahoo.com.brURL: http://repositorio.unicamp.br/jspui/handle/REPOSIP/322436

Min-Based Conditioning of Possibilistic EL Ontology

The EL is a tractable family of lightweight description logics that underlay the OWL EL profile. It guarantees the tractability of the reasoning process, especially for concept classification. In particular, such a fragment is widely used for medical applications. This paper investigates the evolution of EL ontologies when a new piece of information that can be conflicting or attached with a confidence level reflecting its credibility or priority is available. To encode such knowledge, we propose an extension of EL description logic within the possibility theory, which provides a natural way to deal with ordinal scale reflecting ranking between pieces of knowledge. We then show how such a ranking between axioms is induced from the ontology with the presence of new information and study the evolution process at the semantic level. Finally, we propose a polynomial syntactic counterpart of the evolution process while preserving the consistency of the ontology.

Superconductive Logic Using 2ϕ—Josephson Junctions With Half Flux Quantum Pulses

Superconductive logic based on Josephson junctions (JJ) is a promising technology for energy efficient supercomputers and cloud computing. This technology can deliver significant improvements in performance and energy efficiency as compared to CMOS. Superconductive circuits, however, suffer from low density integration as compared to CMOS, primarily due to the limited scalability of the inductors. To improve the scalability of superconductive logic, a logic family based on a novel JJ technology, <inline-formula> <tex-math notation="LaTeX">$2\phi $ </tex-math></inline-formula>-JJ, has been proposed that eliminates the inductors. In this brief, three circuits are presented which exploit this scalable inductor-less technology. This novel <inline-formula> <tex-math notation="LaTeX">$2\phi $ </tex-math></inline-formula>-JJ technology represents the data as half flux quantum (HFQ) pulses, which improves the energy efficiency and speed as compared to standard superconductive logic such as rapid single flux quantum (RSFQ). Unlike RSFQ, the proposed circuits dynamically switch upon receiving an HFQ pulse, saving energy. These <inline-formula> <tex-math notation="LaTeX">$2\phi $ </tex-math></inline-formula>-JJ logic circuits operate 2.25X faster and require 2.6X less energy as compared to RSFQ.

UNDECIDABILITY AND NON-AXIOMATIZABILITY OF MODAL MANY-VALUED LOGICS

AbstractIn this work we study the decidability of a class of global modal logics arising from Kripke frames evaluated over certain residuated lattices, known in the literature as modal many-valued logics. We exhibit a large family of these modal logics which are undecidable, in contrast with classical modal logic and propositional logics defined over the same classes of algebras. This family includes the global modal logics arising from Kripke frames evaluated over the standard Łukasiewicz and Product algebras. We later refine the previous result, and prove that global modal Łukasiewicz and Product logics are not even recursively axiomatizable. We conclude by closing negatively the open question of whether each global modal logic coincides with its local modal logic closed under the unrestricted necessitation rule.

Monteiro's algebraic notion of maximal consistent theory for Tarskian logics

Antonio Monteiro gave a characterization of maximal congruences in certain semisimple varieties in order to present a representation theorem for them. Under specific conditions, this theorem can be presented with the same proof for every semisimple variety considered by him. In this note, we show that this notion of maximal congruence is closely linked to Henkin's notion of maximal theories for certain families of logics from the literature of algebraic logic. To see this relation, we study the class of n-valued Hilbert algebras with supremum enriched with Moisil operators. For this class of algebras, we present a sound and complete propositional and first-order calculus. Moreover, we show how this relation works for logics from semisimple varieties studied in the Monteiro's school. Extending the scope of applications, we present soundness and completeness results for some first-order paraconsistent logics through non-deterministic matrix semantics. Despite the fact that these logics are not algebraizable with the Blok-Pigozzi's method, they display an algebraic behaviour that allows us to give a simplified presentation.

Algebraizability of the Logic of Quasi-N4-Lattices

The class of quasi-N4-lattices (QN4-lattices) was introduced as a common generalization of quasi-Nelson algebras and N4-lattices, in such a way that N4-lattices are precisely the QN4-lattices satisfying the double negation law (~~x = x) and quasi-Nelson algebras are the QN4-lattices satisfying the explosive law (x ^ ~x) -> y = ((x ^ ~x) -> y) -> ((x ^ ~x) -> y). In this paper we introduce, via a Hilbert-style presentation, a logic (L_QN4) whose algebraic semantics is a class of algebras that we show to be term-equivalent to QN4-lattices. The result is obtained by showing that the calculus introduced by us is algebraizable in the sense of Blok and Pigozzi, and its equivalent algebraic semantics is term-equivalent to the class of QN4-lattices. As a prospect for future investigation, we consider the question of how one could place L_QN4 within the family of relevance logics.

Efficient design of dual‐mode nano counter: An approach using quantum dot cellular automata

AbstractQuantum dot Cellular Automata (QCA) is a promising paradigm after CMOS technology due to low power consumption and small area requirements. As the counter is the most important and fundamental component of the QCA sequential logic family, therefore current effort has been made to design and analysis a dual‐mode counter. The reported dual‐mode nano counter can be operated as a Ring counter (R‐counter) as well as it can be operated as a Twisted‐ring counter (T‐counter). To achieve this, two inverters, four majority voters, and four D flip‐flops have been fully utilized. The main advantage of this design is that a single nano‐counter circuit can perform both tasks of R‐counter and T‐counter, which therefore eliminates the design constraint of double QCA layouts. In addition to that, the proposed 4‐bit QCA layout is easily expandable to n‐bit as per needs. With compared to the best‐reported design, the proposed dual‐mode counter has 75% and 29% less delay and cell count respectively. The area‐delay cost, QCA‐specific cost, and energy‐delay cost of the proposed circuit are approximately 13 times, 228 times, and 61 times superior to the previously reported best design. The designs were verified using the popular QCA layout design software QCADesigner 2.0.3. Simultaneously, two energy estimate tools, QCAPro and QCADesigner‐E (QDE), were utilized to investigate the circuits' energy dissipation.

Skyrmions-based logic gates in one single nanotrack completely reconstructed via chirality barrier.

Logic gates based on magnetic elements are promising candidates for logic-in-memory applications with non-volatile data retention, near-zero leakage and scalability. In such spin-based logic devices, however, the multi-strip structure and fewer functions are obstacles to improving integration and reducing energy consumption. Here we propose a skyrmions-based single-nanotrack logic family including AND, OR, NOT, NAND, NOR, XOR and XNOR that can be implemented and reconstructed by building and switching the Dzyaloshinskii-Moriya interaction (DMI) chirality barrier on a racetrack memory. Besides the pinning effect of the DMI chirality barrier on skyrmions, the annihilation, fusion and shunting of two skyrmions with opposite chirality are also achieved and demonstrated via local reversal of the DMI, which are necessary for the design of an engineer programmable logic nanotrack, transistor and complementary racetrack memory.

Low-Latency Adiabatic Quantum-Flux-Parametron Circuit Integrated With a Hybrid Serializer/Deserializer

Adiabatic quantum-flux-parametron (AQFP) logic is an ultra-low-power superconductor logic family. AQFP logic gates are powered and clocked by dedicated clocking schemes using ac excitation currents to implement an energy-efficient switching process, adiabatic switching. We have proposed a low-latency clocking scheme, delay-line clocking, and demonstrated basic AQFP logic gates. In order to test more complex circuits, a serializer/deserializer (SerDes) should be incorporated into the AQFP circuit under test, since the number of input/output (I/O) cables is limited by equipment. Therefore, in the present study we propose and develop a novel SerDes for testing delay-line-clocked AQFP circuits by combining AQFP and rapid single-flux-quantum (RSFQ) logic families, which we refer to as the AQFP/RSFQ hybrid SerDes. The hybrid SerDes comprises RSFQ shift registers to facilitate the data storage during serial-to-parallel and parallel-to-serial conversion. Furthermore, all the component circuits in the hybrid SerDes are clocked by the identical excitation current to synchronize the AQFP and RSFQ parts. We fabricate and demonstrate a delay-line-clocked AQFP circuit (8-to-3 encoder, which is the largest delay-line-clocked circuit ever designed) integrated with the hybrid SerDes at 4.2 K up to 4.5 GHz. Our measurement results indicate that the hybrid SerDes enables the testing of delay-line-clocked AQFP circuits with only a few I/O cables and is thus a powerful tool for the development of very large-scale integration AQFP circuits.

Low Power Adiabetic Logic System for Biomedical Applications

There have been significant advances in sensors and device structures in the medical industry, particularly in implanted medical devices. Increasingly complex electronic circuitry may now be implanted in the human body thanks to compact, high-energy batteries and hermetic packaging. These gadgets must adhere to strict power consumption guidelines due to the battery recharging schedule. Designing energy-efficient circuits and systems becomes increasingly important as a result of this fact. Adiabatic circuits provide a hopeful alternative for traditional circuitry in case of low energy design. Because of power-clock phases synchronization complexity, designing and functionally verifying presenting 4-phase adiabatic circuitry takes longer. Accordingly, multiple clock generators are used typically and can reveal enhanced consumption of energy in the network of clock distribution. Furthermore, they are not suitable for designing in high-speed because of their clock skew management and high complexity issues. In this paper, TMEL (True multi-phase energy recovering logic), the first energyrecovering/adiabatic logic family is presented for biomedical applications, which functions using the scheme multiple-phase sinusoidal clocking. Moreover, a system of SCAL, a source-coupled variation with TMEL having enhanced energy efficiency and supply voltage scalability, is introduced. A novel true multi-phase Approach and Source-coupled adiabatic logic for energy effective communication system is proposed. The adiabatic logic is employed for both write and read side operation. The CMOS inverter is integrated with TMEL cascades, which in turn reduces leakage loss. In SCAL, the optimal performance at any operating circumstance is attained byan adjustable current source in each gate. SCAL, and TMEL, are capable of outperforming existing adiabatic logic families concerning operating speed and energy efficiency. The performance analysis was carried and simulated through 45 nm CMOS inverter in terms of leakage power, delay, and power consumption. In particular, for the clock rates that range from 10 MHz to 200 MHz, the proposed SCAL was more energy-efficient and less dissipative on comparing their pipelined or purely combinational CMOS counterparts. In biomedical equipment, the system may be included into the low-power design since it is energy efficient and very robust. Improvements in VLSI technology, such as increased dynamic range, low-voltage EEPROMs (electrically eraseable programmable ROMs), and specific sensor techniques, are also expected to contribute to advancements in implanted medical devices in the near future.

All-optical frequency-encoded Toffoli gate

Abstract The construction of an all-optical frequency-encoded Toffoli gate employing a reflecting semiconductor optical amplifier (RSOA) is proposed in this article. By establishing fields such as quantum computing, optical quantum computing, quantum-dot cellular automata, and superconducting flux logic family, quantum gates have been proved to perform reliably in the present day. A nonzero-mass electron, on the other hand, moves far slower than a quantum particle with zero rest mass, such as a photon. Photons can also be utilized to store data while being sent. These photon qualities have motivated researchers to create quantum gates in the all-optical domain based on them. The RSOA-based implementation of the Toffoli gate gives a significant improvement in the case of high speed, low power, and fast switching time. MATLAB Simulink (R2018a) software is used to simulate the devised design. The theoretical prediction is satisfied by the simulation results.

Adiabatic quantum-flux-parametron with delay-line clocking: logic gate demonstration and phase skipping operation

Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. The latency of AQFP circuits is relatively long compared to that of other superconductor logic families and thus such circuits require low-latency clocking schemes. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, in which the latency for each logic operation is determined by the propagation delay of the excitation current, and demonstrated a simple AQFP buffer chain that adopts delay-line clocking. However, it is unclear whether more complex AQFP circuits can adopt delay-line clocking. In the present study, we demonstrate AQFP logic gates (AND and XOR gates) that use delay-line clocking as a step towards implementing large-scale AQFP circuits with delay-line clocking. AND and XOR gates with a latency of approximately 20 ps per gate are shown to operate at up to 5 and 4 GHz, respectively, in experiments. We also demonstrate that delay-line clocking enables phase skipping operation, in which some of the AQFP buffers for phase synchronization are removed to reduce the junction count and energy dissipation. The results indicate that delay-line clocking can enable low-latency, low-energy, large-scale AQFP circuits.