Logic Devices Research Articles

Solution‐Processed PTCDI‐C8 Crystalline Wire: Dual Role as Mask and Active Layer for Organic Transistors with Increased Switching Speeds

AbstractOrganic field‐effect transistors (OFETs) have been extensively studied over the past decades because of their suitability for low‐cost, large‐area, and flexible electronics. However, improvements are needed to satisfy the demands of high‐speed applications. The switching speed of a logic device is affected by the charge‐carrier mobility (µ) and the square of the channel length (L) at a given gate–source bias. Therefore, increasing µ and/or reducing L are crucial for achieving high‐speed OFET‐based digital circuits. In this study, an n‐type OFET is fabricated with increased switching speed via a dual‐role approach involving solution‐grown, highly ordered single‐crystalline N,N'‐dioctyl‐3,4,9,10‐perylenetetracarboxylic diimide (PTCDI‐C8) wires, which serve as a mask for short‐channel formation up to the microscale and an active layer with enhanced charge mobility. Additionally, the performance of the n‐type short‐channel OFET and resistive‐load‐type inverters is evaluated. For comparative purposes, long‐channel (50 µm) devices with PTCDI‐C8 wires and short‐channel devices with a PTCDI‐C8 film are fabricated and the device performance is analyzed. The short‐channel device with the PTCDI‐C8 wires exhibits a significantly higher switching speed. Thus, the dual‐role approach is a simple and straightforward method for fabricating short‐channel devices, paving the way for further advancements in OFET technology requiring high switching speeds.

Design and Performance Analysis of Logic Circuits using FinFET Technology

As the dimensions of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) decreases, the short channel effect (SCE) becomes a dominating concern in VLSI. The Short channel effect causes an exponential increase in the leakage current. To reduce the SCE and hence leakage current, a new technology has been developed in recent years. In this recent technology a 3D multiple gate MOSFETs like FinFET (Fin Field Effect Transistor) has been developed which possess numerous advantages over conventional MOSFETs and has attracted many engineers and designers. FinFET is the new growing technology that works in the nm range to minimize short channel effects. Many companies (like Intel) have started using FinFET technology. This document is a review paper of current research on FinFET technology and discusses how it can be used in future to design new logic devices (like Adder, Comparator, MUX and De-MUX etc.) and memory devices. Various parameters of FinFET like reduced short channel effects, less leakage current, low power consumption, less propagation delay and less time delay are discussed. Various mathematical models and software (HSpice) were used to simulate power, delay, power delay product, average power dissipation and energy delay product. Thus, FinFET technology was designed to eliminate the problem of SCE by permitting transistors to be scaled down into sub 20nm range.

Interband transition physics from the absorption edge in GaN: New prospects from numerical analysis

The strong polarization effects and abundant surface states in III-nitrides result in a tunable electric field, modifying the absorption/emission by changing the band structure. Thus, the mechanism of the electric field and the absorption/emission is crucial for future optical logic devices. Here, we propose to extract the information from the absorption/emission edge by numerical simulations. The simulations show that the increase in the field strength would red-shift the spectrum as well as decrease the slope of the edge for both the uniform and non-uniform field. For numerical simulations, we also provide the lower limit of the quantum states to be simulated from Wentzel–Kramers–Brillouin approximation. Then three GaN samples with different n values are analyzed, and the results validate our methods in two ways. On the one hand, the nonuniform field is shown to fit the experimental absorption better at higher n, which is in accordance with previous studies. On the other hand, the reasonable bandgap Eg at zero doping level and the bandgap-renormalization coefficient are obtained. This work would deepen the understanding of the absorption/emission influenced by the electric field and pave the way for numerical analysis of the edge.

Anti-Ambipolar Heterojunctions: Materials, Devices, and Circuits.

Anti-ambipolar heterojunctions are vital in constructing high-frequency oscillators, fast switches, and multivalued logic (MVL) devices, which hold promising potential for next-generation integrated circuit chips and telecommunication technologies. Thanks to the strategic material design and device integration, anti-ambipolar heterojunctions have demonstrated unparalleled device and circuit performance that surpasses other semiconducting material systems. This review aims to provide a comprehensive summary of the achievements in the field of anti-ambipolar heterojunctions. First, the fundamental operating mechanisms of anti-ambipolar devices are discussed. After that, potential materials used in anti-ambipolar devices are discussed with particular attention to 2D-based, 1D-based, and organic-based heterojunctions. Next, the primary device applications employing anti-ambipolar heterojunctions, including anti-ambipolar transistors (AATs), photodetectors, frequency doublers, and synaptic devices, are summarized. Furthermore, alongside the advancements in individual devices, the practical integration of these devices at the circuit level, including topics such as MVL circuits, complex logic gates, and spiking neuron circuits, is also discussed. Lastly, the present key challenges and future research directions concerning anti-ambipolar heterojunctions and their applications are also emphasized.

Simulation Modelling of Silicon Gated Field Emitter Based Electronic Circuits

Vacuum transistors (VTs) are promising candidates in electronics due to their fast response and ability to function in harsh environments. In this study, several oscillator and logic gate circuit simulations using VTs are demonstrated. Silicon-gated field emitter arrays (Si-GFEAs) with 1000 × 1000 arrays were used experimentally to create a VT model. First, transfer and output characteristics sweeps were measured, and based on those data, an LTspice vacuum transistor (VT) model was developed. Then, the model was used to develop Wein and Ring oscillator circuits. The circuits were analytically simulated using LTspice, where the collector bias voltage was 200 V DC, and the gate bias voltage was 30–40 V DC. The Wein oscillator circuit produced a frequency of 102 kHz with a magnitude of 26 Vpp. The Ring oscillator produced a frequency of 1.14 MHz with a magnitude of 4 Vpp. Furthermore, two logic circuits, NOR and NAND gates, were also demonstrated using LTspice modeling. These simulation results illustrate the feasibility of integrating VTs into functional integrated circuits and provide a design approach for future on-chip vacuum transistors applied in logic or radio-frequency (RF) devices.

Skyrmion motion under temperature gradient and application in logic devices

Under the presence of temperature gradient (TG) on a nanotrack, it is necessary to investigate the skyrmion dynamics in various magnetic systems under the combined effect of forces due to magnonic spin transfer torque thermal STT (), entropic difference as well as thermal induced dipolar field (DF). Hence, in this work, the dynamics of skyrmions in ferromagnets (FM), synthetic antiferromagnets (SAF), and antiferromagnets (AFM) have been studied under different TGs and damping constants (). It is observed that plays a major role in deciding the direction of skyrmion motion either towards the hotter or colder side in different magnetic structures. Later, FM skyrmion based logic device is proposed that consists of a cross-coupled nanotrack, where the skyrmions on horizontal and vertical nanotrack are controlled by exploiting TG and electrical STT (eSTT), respectively by taking the advantages of thermal induced skyrmion Hall effect (SkHE). The proposed device performs AND and OR logic functionalities simultaneously, when the applied current density is Moreover, the proposed device is also able to exhibit the half adder functionality by tuning the applied current density to The total energy consumption for AND and OR logic operation and half adder are 33.63 fJ and 25.06 fJ, respectively. This paves the way for the development of energy-efficient logic devices with ultra-high storage density.

Collinear and noncollinear ferrimagnetic phases in Mn4N investigated by magneto-optical Kerr spectroscopy

Ferrimagnetic antiperovskite Mn4N has received growing interest due to room-temperature observation of large perpendicular magnetic anisotropy, low saturation magnetization, and ultrafast response to external magnetic fields. Comprehensive understanding of the underlying magnetic structure is instrumental in design and fabrication of computer memory and logic devices. Magneto-optical spectroscopy provides deeper insight into the magnetic and electronic structure than magnetometry. Simulations of a magneto-optical Kerr effect in biaxially strained Mn4N are performed using density functional theory and linear response theory. We consider three ferrimagnetic phases, two collinear and one noncollinear, which have been investigated separately by earlier studies. The simulated spectra are compared to measured magneto-optical data available in recent literature. One of the collinear ferrimagnetic phases is found to be consistent with the measured spectra. We show that an admixture of the noncollinear phase, which is the ground state of unstrained Mn4N, further improves the agreement with measured spectra, and at the same time, it could explain the lower than predicted net moment and magnetic anisotropy observed in thin films on various substrates.

Stochastic Adder Circuits with Improved Entropy Output.

Random pulse computing (RPC), the third paradigm along with digital and quantum computing, draws inspiration from biology, particularly the functioning of neurons. Here, we study information processing in random pulse computing circuits intended for the summation of numbers. Based on the information-theoretic merits of entropy budget and relative Kolmogorov-Sinai entropy, we investigate the prior art and propose new circuits: three deterministic adders with significantly improved output entropy and one exact nondeterministic adder that requires much less additional entropy than the previous art. All circuits are realized and tested experimentally, using quantum entropy sources and reconfigurable logic devices. Not only the proposed circuits yield a precise mathematical result and have output entropy near maximum, which satisfies the need for building a programmable random pulse computer, but also they provide affordable hardware options for generating additional entropy.

Non‐Volatile Reconfigurable p–n Junction Utilizing In‐Plane Ferroelectricity in 2D WSe2/α‐In2Se3 Asymmetric Heterostructures

AbstractIt is impossible to imagine modern electronic circuitry without a p–n junction—an essential building block for transistors, rectifiers, amplifiers, photovoltaics, etc. Conventional fabrication processes (ion implantation or chemical diffusion) result in an immutable potential configuration depriving reconfigurability. In contrast, the superior electrostatic tunability, dangling bonds‐ and reconstruction‐free interfaces are some of the key features of 2D based heterostructures, making them promising candidates for cutting‐edge optoelectronic and memory applications. Herein, the intercoupled 2D ferroelectricity of 𝛼‐In2Se3 is utilized to introduce micron‐scale, non‐volatile electrostatic doping in ambipolar WSe2, enabling reconfigurable p–n junction. The actuation mechanism is based on the strong polarization field along the edge topology of In2Se3. The fabricated device presents stable p–n to n–p switching, a superior rectification ratio of ≈106, and a low leakage current of ≈10−12 A. Furthermore, the switchable short‐circuit current response is utilized to demonstrate a novel self‐powered, non‐volatile memory based on photovoltaic reading. The ferroelectric non‐volatility coupled with the ability to control the device operation using optical and electrical signals paves the way for ultrathin energy‐efficient, multi‐level optoelectronic and in‐memory logic devices.

Systematical Investigation of Flicker Noise in 14 nm FinFET Devices towards Stochastic Computing Application.

Stochastic computing (SC) is widely known for its high error tolerance and efficient computing ability of complex functions with remarkably simple logic gates. The noise of electronic devices is widely used to be the entropy source due to its randomness. Compared with thermal noise and random telegraph noise (RTN), flicker noise is favored by researchers because of its high noise density. Meanwhile, unlike using RRAM, PCRAM and other emerging memory devices as the entropy source, using logic devices does not require any additional process steps, which is significant for industrialization. In this work, we systematically and statistically studied the 1/f noise characteristics of 14 nm FinFET, and found that miniaturizing the channel area of the device or lowering the ambient temperature can effectively increase the 1/f noise density of the device. This is of great importance to improve the accuracy of the SC system and simplify the complexity of the stochastic number generator (SNG) circuit. At the same time, these rules of 1/f noise characteristics in FinFET devices can provide good guidance for our device selection in circuit design.

Two-dimensional semiconductors based field-effect transistors: review of major milestones and challenges

Two-dimensional (2-D) semiconductors are emerging as strong contenders for the future of Angstrom technology nodes. Their potential lies in enhanced device scaling and energy-efficient switching compared to traditional bulk semiconductors like Si, Ge, and III-V compounds. These materials offer significant advantages, particularly in ultra-thin devices with atomic scale thicknesses. Their unique structures enable the creation of one-dimensional nanoribbons and vertical and lateral heterostructures. This versatility in design, coupled with their distinctive properties, paves the way for efficient energy switching in electronic devices. Moreover, 2-D semiconductors offer opportunities for integrating metallic nanoribbons, carbon nanotubes (CNT), and graphene with their 2-D channel materials. This integration helps overcome lithography limitations for gate patterning, allowing the realization of ultra-short gate dimensions. Considering these factors, the potential of 2-D semiconductors in electronics is vast. This concise review focuses on the latest advancements and engineering strategies in 2-D logic devices.

Large-scale and stacked transfer of bilayers MoS2 devices on a flexible polyimide substrate

Two-dimensional transition metal dichalcogenides (TMDs), as flexible and stretchable materials, have attracted considerable attention in the field of novel flexible electronics due to their excellent mechanical, optical, and electronic properties. Among the various TMD materials, atomically thin MoS2 has become the most widely used material due to its advantageous properties, such as its adjustable bandgap, excellent performance, and ease of preparation. In this work, we demonstrated the practicality of a stacked wafer-scale two-layer MoS2 film obtained by transferring multiple single-layer films grown using chemical vapor deposition. The MoS2 field-effect transistor cell had a top-gated device structure with a (PI) film as the substrate, which exhibited a high on/off ratio (108), large average mobility (∼8.56 cm2 V−1 s−1), and exceptional uniformity. Furthermore, a range of flexible integrated logic devices, including inverters, NOR gates, and NAND gates, were successfully implemented via traditional lithography. These results highlight the immense potential of TMD materials, particularly MoS2, in enabling advanced flexible electronic and optoelectronic devices, which pave the way for transformative applications in future-generation electronics.

Reconfigurable all-optical logic device based on cross-phase modulation across highly non-linear fiber

All-optical logic gates are the basic building blocks of photonic integrated circuits to be used for signal processing, to ensure high speed signal processing and decreasing complexity of network. In this paper, reconfigurable all-optical logic gate has been proposed and numerical simulations are analysed at a bit rate of 120 Gb/s. Wavelength Converter, NOT, NOR, AND, XOR, XNOR, A¯.B and OR are the all-optical logic gates that has been designed and implemented using single circuit and has minimum quality factor of 27 dB. All the signal processing operations have been implemented by the exploitation of cross-phase modulation in two parallelly placed (Mach-Zehnder Interferometric configuration) highly nonlinear fibers (HNLF). The influence of variation in input power, at different length of HNLF determines that the quality factor increases for increase in power or length of highly nonlinear fiber up to a certain limit. Quality factor increases for decrease in effective area of the highly nonlinear fiber for a certain range of input power and saturates for further increase in input power. Also, the quality factor is not directly affected with increase in bit rate but adversely affected by increase in dispersion.

The Amplified DNA Logic Gates Based on Aptamer-Receptor Recognition for Cell Detection and Bioimaging.

A powerful and accurate method for identifying and isolating cells would be of great importance due to its sensitivity, gentleness and effectiveness. Here, we designed a receptor-based DNA logic device that allows Boolean logic analysis of multiple cells. For ease of expression, the molecules on the cell surface that can bind to the aptamer are referred to as "receptors". This DNA logic device sends signals based on cell surface sgc8c and sgc4f receptor expression by performing NOT, NOR, AND and OR logic operations, and amplifies and evaluates the signals using HCR. Meanwhile, the release of ICG from the endopore of HMSNs is controlled by affecting structural changes in the DNA logic device. This approach can accurately identify and treat multiple cells on demand based on the presence or absence of cell-specific receptors, facilitating the development of personalized medicine.

Controlling the Spatial Profile and Energy Landscape of Organic Polariton Condensates in Double-Dye Cavities.

The development of high-speed, all-optical polariton logic devices underlies emerging unconventional computing technologies and relies on advancing techniques to reversibly manipulate the spatial extent and energy of polartion condensates. We investigate active spatial control of polariton condensates independent of the polariton, gain-inducing excitation profile. This is achieved by introducing an extra intracavity semiconductor layer, nonresonant to the cavity mode. Partial saturation of the optical absorption in the uncoupled layer enables the ultrafast modulation of the effective refractive index and, through excited-state absorption, the polariton dissipation. Utilizing an intricate interplay of these mechanisms, we demonstrate control over the spatial profile, density, and energy of a polariton condensate at room temperature.

Vertically Integrated CMOS Ternary Logic Device with Low Static Power Consumption and High Packing Density.

A ternary logic system to realize the simplest multivalued logic architecture can enhance energy efficiency compared to a binary logic system by reducing the number of transistors and interconnections. For the ternary logic system, a ternary logic device to harness three stable states is needed. In this study, a vertically integrated complementary metal-oxide-semiconductor ternary logic device is demonstrated by monolithically integrating a thin-film transistor (TFT) over a transistor-based threshold switch (TTS). Because the TFT and the TTS have their own source (S), drain (D), and gate (G), there are physically six electrodes. But the hybrid ternary logic device of the TFT over the TTS has only four electrodes: S, D, GTFT, and GTTS like a single MOSFET. It is because the D of the underlying TTS is electrically tied with the S of the superjacent TFT. By combining an on- and off-state of the TFT and the TTS, ternary logic values of low current ("0"-state), middle current ("1"-state), and high current ("2"-state) are realized. Particularly, static power consumption at the "1"-state is decreased by employing the TTS with low off-state leakage current compared to previously reported other ternary logic devices. In addition, a footprint of the ternary logic device with the vertically overlaying structure that has a framework of "one over the other" can be lowered by roughly twice compared to that with the laterally deployed structure that has an organization of "one alongside the other".

Highly Reconfigurable Logic‐In‐Memory Operations in Tunable Gaussian Transistors for Multifunctional Image Processing

AbstractReconfigurable logic‐in‐memory device, albeit a promising hardware platform for constructing parallel computing architectures, still suffers from high power‐consumption and low area‐efficiency arising from the circuit redundancy in silicon (Si) based technical path. 2D materials are identified as potential building blocks to significantly reduce the circuit footprints with outstanding power‐efficiency, owing to their atomically thin nature and unique electronic properties. However, the present 2D logic devices are primarily based on single channel materials with homogeneous transport polarities, limiting the device reconfigurability for multi‐functional applications. Here, 2D p–n junction based dual‐gate Gaussian‐type transistors for simplified reconfigurable logic circuits are reported. All fundamental Boolean logic operators are implemented in a single device with electrically driven reconfigurability, giving rise to an ultra‐low transistor consumption down to 13% of the traditional circuits. The device is also demonstrated as a reliable image processing unit for various computing tasks (pixel processing, comparing, and ciphering) by executing the corresponding logic operations. Moreover, in situ memory of the Boolean logics is achieved by engineering the dielectric properties of the transistor without compromising its reconfigurability. These findings provide a potential approach to achieving reconfigurable logic‐in‐memory operations at the hardware level, with significant implications for the advancement of parallel computing.

Self-Checking Combinational Devices Synthesis Based on the Boolean Signal Correction Method Using Bose—Lin Codes

An organizing concurrent error-detection (CED) circuit new method for automation and computer technology combinational device is considered. The method based on the signal's Boolean correction method. The author proposed to use separable codes in the CED circuit synthesis when converting values from all operational outputs of the diagnosing object. The proposed approach allows to consider many possible transformations for each input combination. In addition, it will allow to choose the transformations to provide the conditions for building a completely self-checking device. In comparison with the methods previously discussed in the literature, the proposed approach makes it possible to synthesize a large number of control logic devices in the CED circuit and choose the most appropriate option. For example, with the technical implementation complexity lowest indicators. An algorithm for synthesizing the control logic block is given on the example of using a separable Bose — Lin code with module M = 4 by the signals Boolean correction method when organizing an CED circuit. The proposed method advantages and disadvantages for the CED circuit synthesis are described.

A spatially-controlled DNA triangular prism nanomachine for AND-gated intracellular imaging of ATP in acidic microenvironment.

ADNA triangular prism nanomachine (TPN)-based logic device for intracellular AND-gated imaging of adenosine triphosphate (ATP)has been constructed. By using i-motif sequences and ATP-binding aptamers as logic control units, the TPN logic device is qualified to respond to the acidic environment and ATP in cancer cell lysosomes. Once internalized into the lysosome, the specific acidic microenvironment in lysosome causes the i-motif sequence to fold into a tetramer, resulting in compression of DNA tri-prism. Subsequently, the split ATP aptamer located at the tip of the collapsed triangular prism binds stably to ATP, which results in the fluorescent dyes (Cy3 and Cy5) modified at the ends of the split aptamer being in close proximity to each other, allowing Förster Resonance Energy Transfer (FRET) to occur. The FRET signals are excited at a wavelength of 543 nm and can be collected within the emission range of 646-730 nm. This enables the precise imaging of ATP within a cell. We also dynamically operate AND logic gates in living cells by modulating intracellular pH and ATP levels with the help of external drugs. Owing to the AND logic unit on TPN itcan simultaneously recognize two targets and give corresponding intelligent logic judgment via imaging signal output. Theaccuracy of molecular diagnosis of cancer can be improved thuseliminating the false positive signal of single target-based detection. Hence, this space-controlled TPN-based logical sensing platform greatly avoids sensitivity to extracellular targets during the cell entry process, providing a useful tool for high-precision imaging of the cancer cell's endogenous target ATP.

TEST GRAPH-SCHEMES OF THE ALGORITHMS OF FINITE STATE MACHINES WORK FOR ASSESSING THE EFFICIENCY OF AUTOMATED SYNTHESIS IN XILINX VIVADO CAD

Context. The problem of evaluating the effectiveness of the automated design of a microprogram finite state machine with the operational transformation of state codes using Xilinx Vivado CAD is considered. The object of the research was graph-schemes of control algorithms implemented by finite state machine and able to prove the effectiveness of the principle of operational transformation of state codes in comparison with standard synthesis methods built into the CAD, in the context of hardware expenses optimization.
 Objective. Development and research of graph-schemes of control algorithms in order to substantiate the effectiveness of the application of structure of the finite state machine with datapath of transitions in comparison with the built-in methods of synthesizing finite state machines in Xilinx Vivado CAD in the basis of programmable logic devices.
 Method. The research is based on the hypothetical assumption that the Xilinx Vivado CAD has built-in methods of automated design of the circuit of a finite state machine, the effectiveness of which, according to the criterion of hardware expenses, exceeds other known methods of optimizing hardware expenses in the finite state machine circuit. In order to refute this hypothesis, it is proposed to prove that in some cases known methods of hardware expenses optimization in the finite state machine circuit are more effective in comparison with the methods built into CAD. In this work, as a well-known optimization method, the method of operational transformation of state codes, which corresponds to the structure of a finite state machine with datapath of transitions, is chosen. The effectiveness of this method is demonstrated on the example of several test graph-schemes of algorithms, the structure of which is abstract and artificially adapted to the chosen optimization method. The adaptation of the selected graph-schemes of the algorithms consists in the fact that a relatively small number of transition operations is required for their implementation with the help of a finite state machine with datapath of transitions. This contributes to the simplification of the circuit of the finite state machine and the reduction of hardware costs for its implementation. At the same time, the test graph-schemes of the algorithms have the possibility of scaling, which allows to automate the construction of VHDL models of the corresponding finite state machines for graph-schemes of different sizes and to evaluate the optimization of hardware expenses for finite state machines of different complexity.
 Results. Using the example of several graph-schemes of algorithms, it is demonstrated that in some cases none of the finite state machine synthesis methods built into the Xilinx Vivado CAD is able to surpass the method of operational transformation of state codes according to the criterion of hardware expenses for the implementation of a finite state machine circuit. At the same time, a several-fold gain in hardware expenses can be achieved, which indicates the expediency of using this method under certain conditions. The formal definition of such conditions for the considered and other known optimization methods is a separate unsolved scientific problem.
 Conclusions. The conducted experiments confirmed that in some cases, the known methods of synthesis of finite state machines allow to obtain circuits with lower hardware expenses than when using the methods of synthesis of finite state machines contained in Xilinx Vivado CAD. This testifies to the general expediency of using existing and developing new methods of hardware expenses optimization in the circuit of the finite state machines and the current relevance of the theory of the synthesis of digital automata as a scientific direction.