CMOS Logic Process Research Articles

DAM SRAM CORE: An Efficient High-Speed and Low-Power CIM SRAM CORE Design for Feature Extraction Convolutional Layers in Binary Neural Networks.

This article proposes a novel design for an in-memory computing SRAM, the DAM SRAM CORE, which integrates storage and computational functionality within a unified 11T SRAM cell and enables the performance of large-scale parallel Multiply-Accumulate (MAC) operations within the SRAM array. This design not only improves the area efficiency of the individual cells but also realizes a compact layout. A key highlight of this design is its employment of a dynamic aXNOR-based computation mode, which significantly reduces the consumption of both dynamic and static power during the computational process within the array. Additionally, the design innovatively incorporates a self-stabilizing voltage gradient quantization circuit, which enhances the computational accuracy of the overall system. The 64 × 64 bit DAM SRAM CORE in-memory computing core was fabricated using the 55 nm CMOS logic process and validated via simulations. The experimental results show that this core can deliver 5-bit output results with 1-bit input feature data and 1-bit weight data, while maintaining a static power consumption of 0.48 mW/mm2 and a computational power consumption of 11.367 mW/mm2. This showcases its excellent low-power characteristics. Furthermore, the core achieves a data throughput of 109.75 GOPS and exhibits an impressive energy efficiency of 21.95 TOPS/W, which robustly validate the effectiveness and advanced nature of the proposed in-memory computing core design.

High-density via RRAM cell with multi-level setting by current compliance circuits

In this work, multi-level storage in the via RRAM has been first time reported and demonstrated with the standard FinFET CMOS logic process. Multi-level states in via RRAM are achieved by controlling the current compliance during set operations. The new current compliance setting circuits are proposed to ensure stable resistance control when one considers cells under the process variation effect. The improved stability and tightened distributions on its multi-level states on via RRAM have been successfully demonstrated.

Design of Processing-in-Memory With Triple Computational Path and Sparsity Handling for Energy-Efficient DNN Training

As machine learning (ML) and artificial intelligence (AI) have become mainstream technologies, many accelerators have been proposed to cope with their computation kernels. However, they access the external memory frequently due to the large size of deep neural network model, suffering from the von Neumann bottleneck. Moreover, as privacy issue is becoming more critical, on-device training is emerging as its solution. However, on-device training is challenging because it should perform the training under a limited power budget, which requires a lot more computations and memory accesses than the inference. In this paper, we present an energy-efficient processing-in-memory (PIM) architecture supporting end-to-end on-device training named T-PIM. Its macro design includes an 8T-SRAM cell-based PIM block to compute in-memory <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AND</i> operation and three computational datapaths for end-to-end training. Each of three computational paths integrates arithmetic units for forward propagation, backward propagation, and gradient calculation and weight update, respectively, allowing the weight data stored in the memory stationary. T-PIM also supports variable bit precision to cover various ML scenarios. It can use fully variable input bit precision and 2-bit, 4-bit, 8-bit, and 16-bit weight bit precision for the forward propagation and the same input bit precision and 16-bit weight bit precision for the backward propagation. In addition, T-PIM implements sparsity handling schemes that skip the computation for input data and turn off the arithmetic units for weight data to reduce both unnecessary computations and leakage power. Finally, we fabricate the T-PIM chip on a 5.04mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die in a 28-nm CMOS logic process. It operates at 50–280MHz with the supply voltage of 0.75–1.05V, dissipating 5.25–51.23mW power in inference and 6.10–37.75mW in training. As a result, it achieves 17.90–161.08TOPS/W energy efficiency for the inference of 1-bit activation and 2-bit weight data, and 0.84–7.59TOPS/W for the training of 8-bit activation/error and 16-bit weight data. In conclusion, T-PIM is the first PIM chip that supports end-to-end training, demonstrating 2.02 times performance improvement over the latest PIM that partially supports training.

200-MHz Single-Ended 6T 1-kb SRAM With 0.2313 pJ Energy/Access Using 40-nm CMOS Logic Process

A high-speed and low energy-consuming SRAM design based on single-ended cells is demonstrated in this work. To resolve poor SNM (static noise margin) of prior single-ended memory cells, the proposed SRAM cell is equipped with a pull-up PMOS and a high-Vthn NMOS foot switch such that the cell state is not bothered by noise when the supply voltage is getting lowered. Moreover, a PFOS (Positive Feedback Op-Amp Sensing) circuit is added between bitlines ( BL̅, BL) to reduce the read delay and generate full-swing output. Last but not least, a voltage mode select (VMS) circuit is added to each column to reduce the static power of unselected cells such that idle power is drastically reduced. The reason is that the a lower voltage able to keep the state of bits is applied to those unselected cells. A 1-kb SRAM prototype based on the proposed cells with BIST (build-in self test) circuit is physically fabricated using typical 40-nm CMOS logic process. The maximum operating clock rate is 200 MHz. The energy/access and energy/bit are measured on silicon to be 0.2313 pJ, and 0.00723 pJ, respectively.

A CIM-Digital Heterogeneous Accelerating System with Analog Interconnection for Neural Networks

In recent years, computing in memory (CIM) has been regarded as a promising competitor for low-power accelerators for neural networks. Different implementations based on various memories like ReRAM and flash memory have been proposed. However, a ‘cloud’ is hovering on the horizon of CIM. The limited frequency and high power consumption of DACs and ADCs have become major obstacles of further improvement of the power efficiency of CIM accelerators. The method of utilizing a more advanced process to increase the frequency and reduce the power consumption of DACs and ADCs can hardly be used because of the tight coupling of memory process and CMOS logic process in CIM accelerators. To solve this problem, this paper proposes a CIM-digital heterogeneous neural network accelerating system with analog interconnection. It decouples the CMOS logic process and the memory process in CIM accelerators by using analog interconnection, and implements ADCs and other units in an independent CMOS process. According to experimental results, compared to prior CIM accelerators, the proposed architecture can achieve an increase in the sampling rate of 26.7 times, to 100 MHz, and an increase in the performance of 26.7 times accordingly. The power efficiency can be improved 5.8 times.

Cost-Effective 4 GHz VCO Using Only Miniature Spirals Realized in a 0.18 μm CMOS Process for Wireless Sensor Network (WSN) Applications

This paper presents an extremely cost-effective radio-frequency integrated circuit (RFIC) implementation technique by employing a digital logic CMOS process and reducing area occupation for voltage-controlled oscillators (VCOs) using all miniature inductors for wireless sensor network (WSN) applications. The designed VCO operates in the 4.0 GHz band with a power consumption of 1.4 mW and a phase noise of −113.6 dBc/Hz at 1 MHz, occupying a Si area of 0.283 × 0.682 mm2. In addition, we confirmed that the figure of merit (FOM) of 183.8 in our design is competitive with that of other LC-VCOs that were fabricated using the RF option and designed with conventional inductors.

Analyzing the Monolithic Integration of a ReRAM-Based Main Memory Into a CPU's Die

Nonvolatile memory, such as resistive RAM (ReRAM), is compatible with standard CMOS logic processes, allowing a sizable main memory system to be integrated into a CPU's die. ReRAM bitcells are fabricated within crosspoint subarrays that leave the bulk of transistors underneath the subarrays vacant. This permits placing the memory system over the CPU, improving area, parallelism, and power. Our work quantifies the impact of integrating ReRAM into a CPU's die. When integrating ReRAM over CPU logic, the best area efficiency occurs when 48% of the die is covered with ReRAM. The CPU's area increases by 18.8%, but we can recoup 35.5% of the die area by utilizing the free transistors underneath the crosspoint subarrays. When integrating ReRAM over CPU cache, up to 85.3% of the cache can be covered with ReRAM. Our work also shows that on-die ReRAM can support very high bandwidth through massively parallel memory access. At 28 nm, 4–16k independent ReRAM banks could be integrated onto the CPU die, providing 512–1024–GB/s peak bandwidth. At more advanced technology nodes, 5–10 TB/s may be possible.

A 28-nm 320-Kb TCAM Macro Using Split-Controlled Single-Load 14T Cell and Triple-Margin Voltage Sense Amplifier

Ternary content-addressable memory (TCAM) is limited by large cell area, high search power, significant active-mode leakage current, and a tradeoff between search speed and signal margin on the match-line (ML). In this paper, we developed a split-controlled single-load 14T (SCSL-14T) TCAM cell and a triple-margin voltage sense amplifier (TM-VSA) to achieve the following: 1) compact cell area; 2) lower search delay and search energy; 3) reduced current leakage in standby and active modes; and 4) tolerance for small sensing margin. A testchip with 320-Kb 14T-TCAM macro was fabricated using a 28-nm CMOS logic process and modified compact foundry six-transistor (6T) cell. The proposed macro achieved search delay of only 710 ps and 0.422 fJ/bit/search.

A 7T-SRAM With Data-Write Technique by Capacitive Coupling

A 7-transistor static random access memory (SRAM), in which cell data are written by capacitive coupling, is proposed. In the 7T-SRAM configuration, the traditional read/write port using two pass-gates (PGs), which are used in 6T-SRAM, is eliminated and the read port using two transistors such as 8T-SRAM and the equalizer for the cell node pair are installed. This read port transistor also acts as a coupling capacitor for writing external data after floating paired cell nodes. The elimination of current-drive via PGs in read/write operation solves current-conflict problems. No degradation of static noise margin (SNM) reduces V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> minimum by 0.1 V in 24-nm 3.3-V high-voltage CMOS process and by 0.3 V in 40-nm standard logic CMOS process. A large coupling transistor design enhances differential cell signal in write, and enables stable operation for scaled SRAMs with large threshold voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> variation. A 7T-SRAM cell size is comparable to that of 6T-SRAM in 24-nm 3.3-V high-voltage CMOS process and 10% smaller than that of 8T-SRAM in 40-nm standard logic CMOS process. A prototype of 64-b 7T-SRAM with 8.74 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> cell size using 24-nm 3.3-V high-voltage CMOS process has been demonstrated for resistive nonvolatile RAM (NVRAM) page buffer application. The 7T-SRAM macro has achieved 20-ns/10-ns cycle time and 18-ns/10-ns access time at 1.5 V/1.8 V V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> , and also has realized 100% macro yield in a wafer and low soft error rate (SER) of 400 FIT/Mb at 1.6-V V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> minimum, which is equal to |V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">tp</sub> | + |V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">tn</sub> | for 0.1-μA low standby current.

Automotive Reliable Memories Integrated into an Ultra-Low Power 40 nm CMOS Logic Process

Automotive Reliable Memories Integrated into an Ultra-Low Power 40 nm CMOS Logic Process

Twin-bit via resistive random access memory in 16 nm FinFET logic technologies

A via resistive random access memory (RRAM) cell fully compatible with the standard CMOS logic process has been successfully demonstrated for high-density logic nonvolatile memory (NVM) modules in advanced FinFET circuits. In this new cell, the transition metal layers are formed on both sides of a via, given two storage bits per via. In addition to its compact cell area (1T + 14 nm × 32 nm), the twin-bit via RRAM cell features a low operation voltage, a large read window, good data retention, and excellent cycling capability. As fine alignments between mask layers become possible, the twin-bit via RRAM cell is expected to be highly scalable in advanced FinFET technology.

1-kb FinFET Dielectric Resistive Random Access Memory Array in $1\times $ nm CMOS Logic Technology for Embedded Nonvolatile Memory Applications

A new two-transistor logic resistive random-access memory (RRAM) cell with a 16-nm standard FinFET CMOS logic platform that is fully compatible with the CMOS process is proposed and demonstrated in a 1-kb FinFET dielectric RRAM (FIND RRAM) array. The new 16-nm FIND RRAM comprises two logic standard FinFET transistors with a HfO2-based composite resistive gate dielectric film as the storage node in a cell. The set and reset characteristics of the FIND RRAM are largely improved by the locally enhanced field at fin corners, which results in low set voltage and low reset current in array operations. Due to adoption of a FinFET CMOS logic process without any additional masks or processing steps, FIND RRAM can be scaled aggressively with a cell size of $288~\text {nm} \times 265$ nm. Low-voltage operation, excellent reliability, and stable low-resistance state/high-resistance state window are realized with the set and reset procedures based on the incremental step pulse programming algorithm, making FIND RRAM a promising embedded nonvolatile memory in the FinFET era.

A 2.71 nJ/Pixel Gaze-Activated Object Recognition System for Low-Power Mobile Smart Glasses

A low-power object recognition (OR) system with intuitive gaze user interface (UI) is proposed for battery-powered smart glasses. For low-power gaze UI, we propose a low-power single-chip gaze estimation sensor, called gaze image sensor (GIS). In GIS, a novel column-parallel pupil edge detection circuit (PEDC) with new pupil edge detection algorithm XY pupil detection (XY-PD) is proposed which results in 2.9× power reduction with 16× larger resolution compared to previous work. Also, a logarithmic SIMD processor is proposed for robust pupil center estimation, (1 pixel error, with low-power floating-point implementation. For OR, low-power multicore OR processor (ORP) is implemented. In ORP, task-level pipeline with keypoint-level scoring is proposed to reduce the number of cores as well as the operating frequency of keypoint-matching processor (KMP) for low-power consumption. Also, dual-mode convolutional neural network processor (CNNP) is designed for fast tile selection without external memory accesses. In addition, a pipelined descriptor generation processor (DGP) with LUT-based nonlinear operation is newly proposed for low-power OR. Lastly, dynamic voltage and frequency scaling (DVFS) for dynamic power reduction in ORP is applied. Combining both of the GIS and ORP fabricated in 65 nm CMOS logic process, only 75 mW average power consumption is achieved with real-time OR performance, which is 1.2× and 4.4× lower power than the previously published work.

A 65 nm 0.5 V DPS CMOS Image Sensor With 17 pJ/Frame.Pixel and 42 dB Dynamic Range for Ultra-Low-Power SoCs

Adding vision capabilities to wireless sensors nodes (WSN) for the Internet-of-Things requires imagers working at ultra-low power (ULP) in nanometer CMOS systems-on-chip (SoCs). Such performance can be obtained with time-based digital pixel sensors (DPS) working at ultra-low voltage (ULV), at the expense of lower dynamic range, higher fixed-pattern noise (FPN) and thus poorer image quality. To address this problem, three key techniques were developed in this work for DPS pixels: wide-range adaptive body biasing, low- $R_{{\rm on}}$ gating of the 2-transistor in-pixel comparator and digital readout performing delta-reset sampling with low switching activity and robust timing closure. These concepts were demonstrated by designing and fabricating a 128 $\times$ 128 CMOS image sensor array in a 65 nm low-power CMOS logic process. Operating at 0.5 V, it features an FPN of 0.66%, a dynamic range of 42 dB and a fill factor of 57% with a 4 µm pixel pitch, while consuming only 17 pJ/(frame.pixel) and 8.8 µW at 32 fps. These performances combined with the small silicon area of 0.69 mm 2 makes the imager perfectly suitable for integration in ULP SoCs, targeting WSN applications.

Control Plug Lateral Coupling Memory Cell Utilizing Uniform Channel Fowler–Nordheim Operation

In this letter, we propose a control-plug (CP) structure logic nonvolatile memory (LNVM) fabricated by a standard logic CMOS process for mobile applications with low-power-consumption requirement. The operating concept of this cell is based on the use of a lateral capacitance coupling between a bar-type CP and a floating gate. Owing to the unique bar-type CP-coupling method and CP-sharing cell array structure, the novel cell has a coupling ratio of over 94% with the lowest fill factor of 344 as a Fowler-Nordheim (FN)-operated LNVM. Furthermore, because of the high coupling ratio and divided-bias operating method, this cell utilizes a uniform-channel FN tunneling program and erase method using a 3.3 V logic peripheral overdrive tolerable voltage of 5.5 V.

A New High-Density Twin-Gate Isolation One-Time Programmable Memory Cell in Pure 28-nm CMOS Logic Process

A new and compact high-k dielectric breakdown one-time programmable (OTP) cell in pure 28-nm high-k metal gate (HKMG) process is proposed. By adopting a self-aligned twin-gate isolation (TGI) made by merged gate spacer, the new OTP cell can operate independently with a very small cell area. Fabricated by a pure 28-nm HKMG CMOS logic process, this OTP cell successfully achieves an ultrasmall cell size of 0.0441 μm 2 on 28-nm HKMG CMOS logic platform. Using high-k dielectric breakdown as its program mechanism, the antifuse TGI OTP memory has more than three orders of ON/OFF read window with a low program voltage of 4 V in 20 μs. Furthermore, a highly density 64-kbit TGI OTP array has been fabricated and successfully demonstrates the new superior isolation and reliability performances.

Arsenic Dimer (As2 +) Lightly Doped Drain (LDD) Implantation Study for 20nm Logic Device Development

Process variation presents a significant challenge to future scaling of VLSI technology. Junction depth scaling with small Vth variation is required for the 45 nm technology node and beyond. Variations in MOSFET characteristics due to random dopant fluctuation (RDF) may become a fundamental limit to device scaling and circuit complexity. Arsenic dimer (As2 +) implant has been used for the formation of ultra-shallow source drain extensions for NMOS transistors below 45nm, CMOS logic process. As Dimer requires only half the dose and twice the energy of equivalent As+ so it is more favorable for much lower energy (＜ƒ5KeV) implantation. A comparison of electrical parameters including drive current, Rtotal, junction breakdown voltage, gate to drain overlap capacitance and dopant SMIS profile indicates equivalent process performance for dimer and As+ implantation. However, arsenic dimer implantation showed better Vth mismatch performance than conventional As+ implantation.

Source-side injection single-polysilicon split-gate flash memory

The source-side injection single-polysilicon split-gate NOR (S4-NOR) flash memory is proposed for embedded applications. For the S4-NOR cell, the access and floating gates are patterned on the channel between the source and drain junctions with a gap length of 55 nm using conventional photolithography technology, and the floating gate is capacitively coupled to an n-well memory gate. This technology can improve the compatibility with a single-polysilicon CMOS logic process. The memory cell is programmed within 5 µs with a low drain current of 10 µA, and its program efficiency is insensitive to process parameters except gap length, which are suitable for embedded memories from the process control viewpoint in addition to low power consumption. Good reliability is also realized without the effect of gap oxide leakage. Furthermore, the performance and reliability of the S4-NOR cell can be improved by scaling the logic process without using any special process.

A 6-Gb/s Differential Voltage Mode Driver with Independent Control of Output Impedance and Pre-Emphasis Level

A 6-Gb/s differential voltage mode driver is presented whose output impedance and pre-emphasis level can be controlled independently. The voltage mode driver consists of five binary-weighted slices each of which has four sub-drivers. The output impedance is controlled by the number of enabled slices while the pre-emphasis level is determined by how many sub-drivers in the enabled slices are driven by post-cursor input. A prototype transmitter with a voltage-mode driver implemented in a 65-nm CMOS logic process consumes 34.8-mW from a 1.2-V power supply and its pre-emphasized output signal shows 165-mVpp,diff and 0.56-UI eye opening at the end of a cable with 10-dB loss at 3-GHz.

Integrated Energy-Harvesting Photodiodes With Diffractive Storage Capacitance

Integrating energy-harvesting photodiodes with logic and exploiting on-die interconnect capacitance for energy storage can enable new, ultraminiaturized wireless systems. Unlike CMOS imager pixels, the proposed photodiode designs utilize p-diffusion fingers and are implemented in a conventional logic process. Also unlike specialized solar cell processes, the designs utilize the on-chip metal interconnect to form a diffraction grating above the p-diffusion fingers which also provides capacitive energy storage. To explore the tradeoffs between optical efficiency and energy storage for integrated photodiodes, an array of photovoltaics with various diffractive storage capacitors was designed in a 90-nm CMOS logic process. The diffractive effects can be exploited to increase the photodiodes' response to off-axis illumination. Transient effects from interfacing the photodiodes with switched-capacitor DC-DC converters were examined, with measurements indicating a 50% reduction in the output voltage ripple due to the diffractive storage capacitance. A quantitative comparison between 90-nm and 0.35-μm CMOS logic processes for energy-harvesting capabilities was carried out. Measurements show an increase in power generation for the newer CMOS technology, however at the cost of reduced output voltage. One potential application for the integrated photodiodes is harvesting energy for a subdermal biomedical device.