200-MHz Single-Ended 6T 1-kb SRAM With 0.2313 pJ Energy/Access Using 40-nm CMOS Logic Process

Abstract

A high-speed and low energy-consuming SRAM design based on single-ended cells is demonstrated in this work. To resolve poor SNM (static noise margin) of prior single-ended memory cells, the proposed SRAM cell is equipped with a pull-up PMOS and a high-Vthn NMOS foot switch such that the cell state is not bothered by noise when the supply voltage is getting lowered. Moreover, a PFOS (Positive Feedback Op-Amp Sensing) circuit is added between bitlines ( BL̅, BL) to reduce the read delay and generate full-swing output. Last but not least, a voltage mode select (VMS) circuit is added to each column to reduce the static power of unselected cells such that idle power is drastically reduced. The reason is that the a lower voltage able to keep the state of bits is applied to those unselected cells. A 1-kb SRAM prototype based on the proposed cells with BIST (build-in self test) circuit is physically fabricated using typical 40-nm CMOS logic process. The maximum operating clock rate is 200 MHz. The energy/access and energy/bit are measured on silicon to be 0.2313 pJ, and 0.00723 pJ, respectively.