CMOS Logic Process Research Articles

Proposal of a logic compatible merged-type gain cell for high-density embedded DRAM's

A new structure is proposed for a logic compatible merged-type DRAM gain cell, and device and process simulations are performed to verify the cell operation. This cell enables the realization of the memory cell without direct use of capacitor, and is almost compatible with a conventional CMOS logic process. Therefore, it does not require new materials nor new processing equipment, and can be realized in less than 5% increase in process steps in comparison to the 50%-60% increase or more for logic embedded DRAM's with a one-capacitor+one-transistor cell. It can drastically improve 1 and 0 states' separation due to JFET ON/OFF effect of an n-channel region between two p/sup +/-gate regions. For the investigation of the proposed gain cell, detailed simulation is performed utilizing the simulation system well tuned to the actual 0.25-/spl mu/m logic process technology. Furthermore three transistors are merged into approximately one transistor area minimizing the cell size to almost one transistor area. Nondestructive read-out (NDRO) is possible resulting in smaller read cycle time since it does not need re-writing after reading-out, Smaller access time is also possible due to current sensing instead of charge sensing.

Low power dual-port CMOS SRAM macro design

A novel low power dual-port CMOS SRAM structure is described. The inherent low power advantage is obtained by using current-mode rather than voltage-mode signal transmission. The design of this new dual-port memory cell and current-mode sense amplifier is based on 0.5 µm, 5 V CMOS logic process technology. HSPICE simulations show that the circuits can operate at high speed even if the supply voltage is reduced to 2 V. The dual-port memory cell is most suitable for the design of FIFO buffers.

A single poly EEPROM cell structure for use in standard CMOS processes

A single poly EEPROM cell structure implemented in a standard CMOS Process is developed. It consists of adjacently placed NMOS and PMOS transistors with an electrically isolated common polysilicon gate. The common gate works as a "floating gate". The inversion layer as "control node (gate)". Test chips which were fabricated in a 0.8 /spl mu/m/150 /spl Aring/ standard CMOS logic process showed 5-9 V of threshold voltage shift and more than 10000 cycles of endurance with good data retention under high temperature. This EEPROM cell can be easily integrated with CMOS digital and analog circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>