Lithography Step Research Articles

Fabrication of nonplanar tapered fibers to integrate optical and electrical signals for neural interfaces in vivo.

Implantable multifunctional probes have transformed neuroscience research, offering access to multifaceted brain activity that was previously unattainable. Typically, simultaneous access to both optical and electrical signals requires separate probes, while their integration into a single device can result in the emergence of photogenerated electrical artifacts, affecting the quality of high-frequency neural recordings. Among the nontrivial strategies aimed at the realization of an implantable multifunctional interface, the integration of optical and electrical capabilities on a single, minimally invasive, tapered optical fiber probe has been recently demonstrated using fibertrodes. Fibertrodes require the application of a set of planar microfabrication techniques to a nonplanar system with low and nonconstant curvature radius. Here we develop a process based on multiple conformal depositions, nonplanar two-photon lithography and chemical wet etching steps to obtain metallic patterns on the highly curved surface of the fiber taper. We detail the manufacturing, encapsulation and back end of the fibertrodes. The design of the probe can be adapted for different experimental requirements. Using the optical setup design, it is possible to perform angle selective light coupling with the fibertrodes and their implantation and use in vivo. The fabrication of fibertrodes is estimated to require 5-9 d. Nonetheless, due to the high scalability of a large part of the protocol, the manufacture of multiple fibertrodes simultaneously substantially reduces the required time for each probe. The procedure is suitable for users with expertise in microfabrication of electronics and neural recordings.

Area Selective Atomic Layer Deposition for the Use on Active Implants: An Overview of Available Process Technology.

Area-selective atomic layer deposition (ASD) is a bottom-up process that is of particular importance in the semiconductor industry, as it prevents edge defects and avoids cost-intensive lithography steps. This approach not only offers immense potential for the manufacture of active implants but can also be used to improve them. This review paper presents various processes that can be used for this purpose. It also identifies aspects that shall be considered when implementing such a process for medical applications. For example, the inherent selectivity can be used to produce new biosensors, the passivated ASD can be used to encapsulate polymer-based implants, and the activated ASD can be used to improve electrode performance. Finally, the aspects that shall be considered in a coating for active implants are highlighted. ASD therefore offers great potential for use on active implants.

Beveled microneedles with channel for transdermal injection and sampling, fabricated with minimal steps and standard MEMS technology.

Microneedles hold the potential for enabling shallow skin penetration applications where biomarkers are extracted from the interstitial fluid (ISF) and drugs are injected in a painless and effective manner. To this purpose, needles must have an inner channel. Channeled needles were demonstrated using custom silicon microtechnology, having several needle tip geometries. Nevertheless, all the proposed fabrication sequences are not compatible with mass production based on mature, standard microfabrication techniques. Furthermore, ISF extraction was also demonstrated with channeled needles but under poorly controlled conditions and over long periods of time, the latter being impractical for medical use. A range of factors may impede or slow ISF extraction that require controlled experiments. In this work we address the above tasks in terms of microfabrication sequence design, tip geometry design and experimental validation under controlled conditions. We report the development and fabrication of a silicon channeled microneedle array using conventional, industrial micromechanic processes. With only 2 lithography steps, a hypodermic needle tip profile is achieved. Using the fabricated microneedles, fluid extraction is experimented on chicken skin mockups. Extraction tests are carried out by inducing a controlled pressure gradient between the two ends of the microneedle channels, generated by loading the chip or by applying vacuum to the chip's backside. The extraction of more than 1 μL of fluid in 20 minutes is demonstrated with a maximum applied pressure gradient of 500 mbar. A correlation between the extraction rate efficiency and needles' density is observed, both for short and long extraction times. These results provide the first demonstration of in vitro interstitial fluid collection under controlled experimental conditions using silicon hollow microneedles fabricated with standard micro electro mechanical systems (MEMS) fabrication technology and minimal steps. Based on the obtained data, a comparison is drawn between pressure load and vacuum as drivers for ISF extraction, according to modelling and controlled experiments.

Fabrication-related impurity study of thin superconducting Al films using x-ray absorption spectroscopy

Superconducting aluminum thin films are integral to many astrophysics detector applications. Using x-ray absorption spectroscopy (XAS), we have studied the residues and adsorbates created during various standard lithography and etch steps, which are commonly used to pattern thin aluminum films into device structures. We have observed the formation of aluminum oxide as α-Al2O3 and aluminum fluoride as β-AlF3. We have observed correlations between these XAS signatures and the Al film’s microwave loss due to two-level systems. This study, which guides the way for future device optimization, further explores the chemical impact of different process steps, including standard silicon substrate wafer cleaning processes, sulfur-hexa-fluoride plasma etching, passivation with a fluorocarbon, and exposure to photoresist adhesion promoters during the lithography process with the help of control samples.

Design and fabrication of a sub-3 dB grating coupler on an X-cut thin-film lithium niobate platform.

Thin-film lithium niobate (TFLN) based integrated photonic devices have been intensively investigated due to their promising properties, enabling various on-chip applications. Grating couplers (GCs) are wildly used for their flexibility and high alignment tolerance for fiber-to-chip coupling. However, achieving high coupling efficiency (CE) in TFLN GCs often requires the use of reflectors, hybrid materials, or extremely narrow linewidths of the grating arrays, which significantly increases the fabrication difficulty. Therefore, there is a demand for high-CE GCs on TFLN with simple structure and easy fabrication processes. In this paper, combining process capabilities, we demonstrate a highly efficient apodized GC by linearly optimizing the period length and the fill factor on a 600-nm-thick TFLN platform. Without any reflector or hybrid material, we achieve a remarkable coupling loss of -2.97 dB at 1555 nm on the 600-nm-thick X-cut TFLN platform with only a single lithography and etching step. Our work sets a new benchmark for CE among GCs on the 600-nm-thick TFLN platform.

Low-loss and compact arbitrary-order silicon mode converter based on hybrid shape optimization.

Mode converters (MCs) play an essential role in mode-division multiplexing (MDM) systems. Numerous schemes have been developed on the silicon-on-insulator (SOI) platform, yet most of them focus solely on the conversion of fundamental mode to one or two specific higher-order modes. In this study, we introduce a hybrid shape optimization (HSO) method that combines particle swarm optimization (PSO) with adjoint methods to optimize the shape of the S-bend waveguide, facilitating the design of arbitrary-order MCs featuring compactness and high performance. Our approach was validated by designing a series of 13 μm-long MCs, enabling efficient conversion between various TE modes, ranging from TE0 to TE3. These devices can be fabricated in a single lithography step and exhibit robust fabrication tolerances. Experiment results indicate that these converters achieve low insertion losses under 1 dB and crosstalks below -15 dB across bandwidths of 80 nm (TE0-TE1), 62 nm (TE0-TE2), 70 nm (TE0-TE3), 80 nm (TE1-TE2), 55 nm (TE1-TE3), and 75 nm (TE2-TE3). This advancement paves the way for flexible mode conversion, significantly enhancing the versatility of on-chip MDM technologies.

Self-Aligned Edge Contact Process for Fabricating High-Performance Transition-Metal Dichalcogenide Field-Effect Transistors.

The persistent challenges encountered in metal-transition-metal dichalcogenide (TMD) junctions, including tunneling barriers and Fermi-level pinning, pose significant impediments to achieving optimal charge transport and reducing contact resistance. To address these challenges, a pioneering self-aligned edge contact (SAEC) process tailored for TMD-based field-effect transistors (FETs) is developed by integrating a WS2 semiconductor with a hexagonal boron nitride dielectric via reactive ion etching. This approach streamlines semiconductor fabrication by enabling edge contact formation without the need for additional lithography steps. Notably, SAEC TMD-based FETs exhibit exceptional device performance, featuring a high on/off current ratio of ∼108, field-effect mobility of up to 120 cm2/V·s, and controllable polarity─essential attributes for advanced TMD-based logic circuits. Furthermore, the SAEC process enables precise electrode positioning and effective minimization of parasitic capacitance, which are pivotal for attaining high-speed characteristics in TMD-based electronics. The compatibility of the SAEC technique with existing Si self-aligned processes underscores its feasibility for integration into post-CMOS applications, heralding an upcoming era of integration of TMDs into Si semiconductor electronics. The introduction of the SAEC process represents a significant advancement in TMD-based microelectronics and is poised to unlock the full potential of TMDs for future electronic technologies.

Inverse design of highly-efficient and broadband polarization beam splitter on SOI platform

Polarization beam splitters (PBSs) are essential components in integrated optics, particularly for applications demanding high polarization purity. However, most existing PBS designs rely on complex forward design methods, often constrained by large size and limited performance. In this study, we introduce an inverse design approach based on shape optimization to develop a high-performance PBS on the silicon-on-insulator (SOI) platform. By optimizing the boundary shape, the proposed PBS exhibits low insertion loss (<1.4 dB) and high extinction ratio (>9.2 dB) across a bandwidth range of 65 nm (1500 nm–1565 nm), as confirmed by experimental results. The footprint of the device measures 1.7 × 16 μm2, and the entire structure can be fabricated through a single lithography step. This work holds great promise for the convenient and efficient design of on-chip PBSs.

Low-dispersive silicon nitride waveguide resonators by nanoimprint lithography

In this study, we demonstrate the fabrication of waveguide resonators using nanoimprint technology. Without relying on traditionally costly lithography methods, such as electron-beam lithography or stepper lithography, silicon nitride (Si3N4) resonators with high-quality factors up to the order of 105 can be realized at C-band by nanoimprint lithography. In addition, by properly designing the waveguide geometry, a low-dispersive waveguide can be achieved with waveguide dispersion at around −35 ps/nm/km in the normal dispersion regime, and the waveguide dispersion can be further tuned to be 29 ps/nm/km in the anomalous dispersion regime with the polymer cladding. The tunability of nanoimprinted devices is demonstrated by the aid of microheaters, realizing on-chip optical functionalities. This work offers the potential to fabricate low-dispersive waveguide resonators for integrated modulators and filters in a significantly cost-effective and process-friendly scheme.

Advancing large-scale thin-film PPLN nonlinear photonics with segmented tunable micro-heaters

Thin-film periodically poled lithium niobate (TF-PPLN) devices have recently gained prominence for efficient wavelength conversion processes in both classical and quantum applications. However, the patterning and poling of TF-PPLN devices today are mostly performed at chip scales, presenting a significant bottleneck for future large-scale nonlinear photonic systems that require the integration of multiple nonlinear components with consistent performance and low cost. Here, we take a pivotal step towards this goal by developing a wafer-scale TF-PPLN nonlinear photonic platform, leveraging ultraviolet stepper lithography and an automated poling process. To address the inhomogeneous broadening of the quasi-phase matching (QPM) spectrum induced by film thickness variations across the wafer, we propose and demonstrate segmented thermal optic tuning modules that can precisely adjust and align the QPM peak wavelengths in each section. Using the segmented micro-heaters, we show the successful realignment of inhomogeneously broadened multi-peak QPM spectra with up to 57% enhancement of conversion efficiency. We achieve a high normalized conversion efficiency of 3802% W−1 cm−2 in a 6 mm long PPLN waveguide, recovering 84% of the theoretically predicted efficiency in this device. The advanced fabrication techniques and segmented tuning architectures presented herein pave the way for wafer-scale integration of complex functional nonlinear photonic circuits with applications in quantum information processing, precision sensing and metrology, and low-noise-figure optical signal amplification.

Broadband achromatic thermal metalens with a wide field of view based on wafer-level monolithic processes

We present a monolithic metalens free of chromatic aberration over the 8–12 μm wavelength range for thermal imaging. The metalens consists of nano-donut-pillars for dispersion engineering. The proposed metalens design is based on a telecentric optical system, which effectively eliminates off-focus distortion and aberration, enhancing overall imaging quality. Offering a 90° field of view, the metalens ensures uniform focal spot sizes within a 45° field angle across the working wavelength. This enables the capture of high-quality thermal images with sharp images and minimal distortion. With a diameter of 5.75 mm, the metalens is suitable for integration into commercial thermal imaging cameras. The nano-donut-pillar structure of the metalens allows for relatively straightforward mass production, involving i-line stepper lithography and silicon deep etching processes.

Scaling up multispectral color filters with binary lithography and reflow (BLR).

Efforts to increase the number of filters are driven by the demand for miniaturized spectrometers and multispectral imaging. However, processes that rely on sequential fabrication of each filter are cost ineffective. Herein, we introduce an approach to produce at least 16 distinct filters based on a single low-resolution lithographic step with minimum feature size of 0.6 μm. Distinct from grayscale lithography, we employ standard binary lithography but achieve height variations in polymeric resist through a post-development reflow process. The resulting transparent polymeric films were incorporated in Fabry-Perot cavity structures with cavity thickness ranging from 90 to 230 nm to produce transmittance across the visible spectrum. This binary lithography and reflow (BLR) process demonstrates control of the dielectric layer thickness down to ∼15 nm. This new process provides a cost-effective alternative to traditional techniques in fabricating microscopic transmission filters, and other applications where precise thickness variation across the substrate is required.

Repeated fast selective growth of prepatternable monolayer graphene of electronic quality

Pattern formation is becoming indispensable in many applications of high-quality synthetic graphene. Nevertheless, the use of multiple lithography and etching steps can often degrade the properties of graphene due to residual disorder. Here, we report a facile, selective, and recyclable method for graphene synthesis from acetylene (C2H2) via catalytic chemical vapor deposition on a bimetal catalyst (Cu–Ni alloy). The synergistic pairing of the Cu–Ni alloy and C2H2 facilitates a rapid (ca. 1 min) synthesis of high-quality graphene under an intermediate temperature condition, e.g., 800 °C, that is quite relaxed from the far-flung method based on a Cu–CH4 pair. Prepatterned Cu–Ni alloy not only produces monolayer graphene patterns without any postprocessing but is also detachable from the resultant graphene patterns electrochemically, hinting at catalyst recyclability. Our test device of an organic field-effect transistor based on the prepatterned monolayer graphene outperforms its top-down counterpart that has undergone lithography and etching. Our facile selective growth of prepatternable monolayer graphene at intermediate temperatures, along with catalyst recyclability, may altogether lend adaptability, productivity, and sustainability to graphene-incorporated applications.

High mobility graphene field effect transistors on flexible EVA/PET foils

Monolayer graphene is a promising material for a wide range of applications, including sensors, optoelectronics, antennas, EMR shielding, flexible electronics, and conducting electrodes. Chemical vapor deposition (CVD) of carbon atoms on a metal catalyst is the most scalable and cost-efficient method for synthesizing high-quality, large-area monolayer graphene. The usual method of transferring the CVD graphene from the catalyst to a target substrate involves a polymer carrier which is dissolved after the transfer process is completed. Due to often unavoidable damage to graphene, as well as contamination and residues, carrier mobilities are typically 1000–3000 cm2(Vs)−1 , unless complex and elaborate measures are taken. Here, we report on a simple scalable fabrication method for flexible graphene field-effect transistors that eliminates the polymer interim carrier, by laminating the graphene directly onto office lamination foils, removing the catalyst, and depositing Parylene N as a gate dielectric and encapsulation layer. The fabricated transistors show field- and Hall-effect mobilities of 7000–10 000 cm2(Vs)−1 with a residual charge-carrier density of 2×1011 1 cm−2 at room temperature. We further validate the material quality by terahertz time-domain spectroscopy and observation of the quantum Hall effect at low temperatures in a moderate magnetic field of ∼5 T. The Parylene encapsulation provides long-term stability and protection against additional lithography steps, enabling vertical device integration in multilayer electronics on a flexible platform.

Fluxless Bonding Via In-Situ Oxide Reduction

Today there is a growing need for high performance computing for server, artificial intelligence, cloud, graphics, and other computationally challenging applications. These emerging and growing applications require processors, ASICs, and graphics chips that have extreme computing power. Semiconductor chips are being designed and fabricated for these applications have a need to fit as much computing and support circuitry on them as possible on the die. Because of this these die are becoming large and have higher I/O. However, the chips have a maximum size limitation which is the reticle size of the lithography stepper which is 32 mm X 28 mm. These large die chips also have finer and finer pitch for the I/O interconnects which need to be flip chip assembled by either mass reflow or more and more commonly via thermos-compression bonding. Today these chips are normally have copper pillars with solder caps with a minimum pitch of about 40 um. To put this into perspective a full reticle size die with this I/O pitch would have over 560,000 pillars! There are a number of challenges in assembling a flip chip which has this I/O density. One of the largest challenges to be overcome is caused by the fact that these devices need to be fluxed in order to eliminate oxides from the interconnect interface so the surfaces can wet and bond reliably. This is true whether the devices are mass reflowed or thermos- compression bonded. The fluxing can be accomplished via dipping into a trough filled with flux or by spraying it on the surface of the substrate or wafer before the flip chip bonding. The problem arises because the flux needs to be completely cleaned before the bonded die is under-filled. The reason that the flux needs to be completely cleaned is that the under fill will not adhere to a surface which has any flux residue. If there is underfill residue, the molding process will result in voids near the solder interconnect. If there are voids in the underfill the solder will leak into the voids during the reflow portion of the reliability testing process and the solder will often short to the adjacent interconnect resulting in a failure. One can imagine that cleaning flux residue completely on a die with over 500,000 interconnects that have 40 um or finer pitch would be difficult. In response to this issue flux manufacturers have developed no clean fluxes. However, we have found that while these fluxes do leave less residue. However, the residue that is left is even more difficult to clean. These problems become more extreme as the pitch decreases and the I/O density increases accelerating the need for industry solutions. There are 2 potential solutions to this issue that are being develop in the industry. First there has been R&amp;D activity to eliminate solder by developing Cu to Cu interconnect technology. This would eliminate the requirement for fluxing and facilitate the transition to finer and finer pitches. Another method is to develop a method to eliminate oxide on solder other than by using flux. We have been developing such a solution by using Formic Acid vapor oxide reduction in- situ to clean the oxide directly and immediately before thermo-compression bonding by injecting formic acid vapor onto the surfaces directly on the bonding machine, cleaning and eliminating the oxides so that flux is not required. The developed solution consists of a Shroud that fits over a standard TCB bondhead. The shroud has 3 distinct chambers. The first to deliver the formic acid vapor, the next consists of a vacuum exhaust, and the third is a Nitrogen shield, which prevents the gas from getting into the factory environment. This creates a mini environment that can clean oxides from the solder for robust bonding. This presentation will show the design of the oxide reducing gas, discuss experimental data on oxide cleaning parameters and cleaning times, and provide a set of data to clarify the performance of the fluxless process. Additionally, future applicability of the process technology for Cu to Cu interconnect will be discussed. Experimental data showing Cu to Cu interconnect on various devices will be shown that have promising results.

Flexible nanoimprint lithography enables high-throughput manufacturing of bioinspired microstructures on warped substrates for efficient III-nitride optoelectronic devices

III-nitride materials are of great importance in the development of modern optoelectronics, but they have been limited over years by low light utilization rate and high dislocation densities in heteroepitaxial films grown on foreign substrate with limited refractive index contrast and large lattice mismatches. Here, we demonstrate a paradigm of high-throughput manufacturing bioinspired microstructures on warped substrates by flexible nanoimprint lithography for promoting the light extraction capability. We design a flexible nanoimprinting mold of copolymer and a two-step etching process that enable high-efficiency fabrication of nanoimprinted compound-eye-like Al2O3 microstructure (NCAM) and nanoimprinted compound-eye-like SiO2 microstructure (NCSM) template, achieving a 6.4-fold increase in throughput and 25% savings in economic costs over stepper projection lithography. Compared to NCAM template, we find that the NCSM template can not only improve the light extraction capability, but also modulate the morphology of AlN nucleation layer and reduce the formation of misoriented GaN grains on the inclined sidewall of microstructures, which suppresses the dislocations generated during coalescence, resulting in 40% reduction in dislocation density. This study provides a low-cost, high-quality, and high-throughput solution for manufacturing microstructures on warped surfaces of III-nitride optoelectronic devices.

Self‐Aligned Photonic Defect Microcavity Lasers with Site‐Controlled Quantum Dots

AbstractSelf‐assembled semiconductor quantum dots face challenges in terms of scalable device integration because of their random growth positions, originating from the Stranski–Krastanov growth mode. Even with existing site‐controlled growth techniques, for example, nanohole or buried stressor concepts, a further lithography and etching step with high spatial alignment requirements is necessary to accurately integrate quantum dots into the nanophotonic devices. Here, the fabrication and characterization of strain‐induced site‐controlled microcavities are reported, where site‐controlled quantum dots are positioned at the antinode of the optical mode field in a self‐aligned manner without the need of any further nano‐processing. It is shown that the cavity properties such as Q‐factor, mode volume, and mode splitting can be tailored by the geometry of the integrated buried stressor, with an opening &lt;4 µm. The experimental results are complemented with theory calculations based on continuum elasticity. Lasing signatures, including super‐linear input‐output response and linewidth narrowing, are observed for a 3.6‐µm self‐aligned cavity with a Q‐factor of 18 000. Furthermore, the quasi‐planar site‐controlled cavities exhibit no detrimental thermal effects. This approach integrates seamlessly with the industrial‐matured manufacturing process and the buried‐stressor technique, paving the way for exceptional scalability and straightforward manufacturing of high‐β microlasers and bright quantum light sources.

Nanoimprint lithography for grayscale pattern replication of MEMS mirrors in a 200 mm wafer

In this work a multilevel nanoimprint lithography (NIL) replication process was demonstrated to produce 1D MEMS mirrors employing vertical asymmetric comb-drive electrostatic actuation, in a 200 mm wafer SOI-based process. In comparison with a direct write laser (DWL) grayscale lithography step (which for the proposed layout requires around 40 h of exposure time per wafer), this NIL method greatly enhances fabrication throughput by reliably reproducing a master's multilevel topography onto the photoresist. This study describes the NIL master fabricated using grayscale lithography, the working stamp, and the replication micromachining processes. An extensive characterization of the morphology and topography of the intermediate working stamp is provided, along with an optimization study of the replica fabrication and the alignment procedure between the replica and the mirror substrate. The MEMS device pattern was effectively replicated, exhibiting electrode gaps of 3.66 μm (grayscale process yields gaps of 3.5 μm). Discrete photoresist levels of 1.53 μm and 2.83 μm were observed, with a misalignment to the preceding metal layer of 5 μm and 10 μm in the x and y directions, respectively. These deviations were found to be within the required alignment margin defined by the layout (20 μm). The 1D MEMS mirror fabricated using this NIL process was successfully characterized using Scanning Laser-Doppler Vibrometry under atmospheric pressure conditions. The results obtained were in accordance with the theoretical design parameters, demonstrating that NIL can be successfully used as a fast, low-cost alternative lithography process to fabricate multilevel MEMS structures.

CMOS-compatible 6-inch wafer integration of photonic waveguides and uniformity analysis.

In this work, we demonstrate photonic fabrication by integrating waveguide resonators and groove structures using cost-effective i-line stepper lithography on a 6-inch full wafer. Low-loss silicon nitride (SiN) waveguide can be realized with the quality (Q) factor of waveguide resonators up to 105. In addition, groove structures are also integrated by the full-wafer process, providing long-term stability of coupling and package solutions. The uniformity of different die locations is verified within the full wafer, showing the good quality of the fabricated photonic devices. This process integration of photonic devices provides the potential for mass-productive, high-yield, and high-uniformity manufacturing.

Mechanically processed, vacuum- and etch-free fabrication of metal-wire-embedded microtrenches interconnected by semiconductor nanowires for flexible bending-sensitive optoelectronic sensors.

We demonstrate the facile fabrication of metal-wire-embedded microtrenches interconnected with semiconducting ZnO nanowires (ZNWs) through the continuous mechanical machining of micrograting trenches, the mechanical embedding of solution-processable metal wires therein, and the metal-mediated hydrothermal growth of ZNWs selectively thereto. The entire process can be performed at room or a very low temperature without resorting to vacuum, lithography, and etching steps, thereby enabling the use of flexible polymer substrates of scalable sizes. We optimize the fabrication procedure and resulting structural characteristics of this nanowire-interconnected flexible trench-embedded electrode (NIFTEE) architecture. Specifically, we carefully sequence the coating, baking, and doctor-blading of an ionic metal solution for the embedding of clean metal wires, and control the temperature and time of the hydrothermal ZNW growth process for faithful interconnections of such trench-embedded metal wires via high-density ZNWs. The NIFTEE structure can function as a bending-sensitive optoelectronic sensor, as the number of ZNWs interconnecting the neighboring metal wires changes upon mechanical bending. It may benefit further potential applications in diverse fields such as wearable technology, structural health monitoring, and soft robotics, where bending-sensitive devices are in high demand.