Leakage Current Compensation Research Articles

A low-noise, radiation-hardened charge-sensitive amplifier for Silicon carbide neutron detector

Silicon carbide(SiC) neutron detectors can be applied to extreme environments with high temperature and strong radiation. The total noise factor is most significantly influenced by the noise factor of the first stage in a cascade amplifier. Hence, the preamplifier must exhibit exceptional noise performance. The readout circuit is inevitably exposed to the influence of radiation, which may result in temporary or even permanent failure of electronic systems. The connection method between the SiC neutron detector and the readout circuit is typically DC-coupled. When the sensor is working, the leakage current generated by the sensor will enter the input end of the CSA and change the baseline position of the CSA. In this paper, a low-noise CSA with leakage current compensation circuit(LCC) is presented. The circuit’s voltage-to-charge amplification is 2.98mV/fC, and the error due to nonlinearity is below 0.01%. Without considering the input parasitic capacitance, ENC is 43.12e-. In addition, the circuit also has good radiation resistance and leakage current compensation function. It is implemented and simulated in the DB Hitek 0.18μm CMOS process model.

Circuit design of a novel front readout circuit for SiC neutron detector with leakage current compensation

Radiation detectors have broad application prospects in environmental radiation monitoring, radiation source identification, biomedical imaging, space exploration, astrophysics, other radiation detection and imaging fields. Among the third generation semiconductors, the properties of 4H-SiC are more suitable for making high-temperature and strong radiation neutron detectors. SiC materials have become a current research hotspot. In this paper a special readout integrated circuit is designed for the extremely weak current pulse signal output by SiC trench neutron detector. A leakage current compensation circuit is designed for the influence of leakage current on charge sensitive amplifier(CSA) output baseline. The noise of CSA output is analyzed and the noise minimization is carried out. The circuit can quickly respond to the input signal and extract the energy and time information. The circuit is designed based on the DB Hitek 0.18μm CMOS process model. The layout design is achieved and the post-simulation is completed. Simulated results show that the equivalent input charge range of the system is about 2fC ∼ 20fC. The charge conversion gain is 88mV/fC. The nonlinear error is within 1.6 %. Moreover, the equivalent noise charge is 22e-. The circuit has the advantages of high gain, high linearity and low noise. Therefore, the circuit can effectively adapt to the characteristics of the charge signal output from SiC trench neutron detectors and amplify the output charge signal.

A simulator for Timepix-like pixel front-ends

This work presents the development of a front-end simulation code for the Timepix3 readout chip [1], intended as digitizer stage in full detector simulation. The front-end electronics is modelled using an integrator stage and 3 parallel feedback loops with individually configurable time constants. The main feedback discharging the integrator consists of 3 low-pass filtered feedback loops. The leakage current compensation is approximated by an additional independent low-pass filtered feed-back loop. The system noise is modelled using independent bandwidth limited noise channels for pre-amplifier, feedback and threshold noise. The Timepix3 time of arrival (ToA) and time over threshold (ToT) measurement is implemented by a discriminator model with independent rise and fall times and 2 independent clock frequencies for ToA and ToT. The measured dependence of the ToT on the pre-amplifier input charge using test-pulses of a Timepix3 assembly is correctly reproduced for a wide range of discriminator settings.

A 8.1-nW, 4.22-kHz, −40–85 °C relaxation oscillator with subthreshold leakage current compensation and forward body bias buffer for low power IoT applications

This paper presents a relaxation oscillator (RxO) utilizing subthreshold transistor leakage current compensation (SLC) technology to expand the operating range from 70 °C to 85 °C at high temperatures. The compensated RxO outperforms the uncompensated counterpart by 25 times for temperature coefficient (TC). Additionally, forward body bias (FBB) technology optimizes the digital buffer delay with temperature drift at low supply voltage, extending the oscillator’s low-temperature range from −20 °C to −40 °C. Fabricated in a 65 nm CMOS process, the oscillator consumes a mere 8.1 nW at a 0.4 V supply voltage. At room temperature, it operates at 4.22 kHz with an energy efficiency of 1.92 nW/kHz. The oscillator demonstrates a temperature coefficient (TC) of 114.01 ppm/°C within the range of −40 °C to 85 °C, rendering it a prospective choice for low-power Internet of Things (IoT) applications.

SPHIRD–Single Photon Counting Pixel Readout ASIC With Pulse Pile-Up Compensation Methods

This paper presents the design and measurement results of a prototype SPHIRD-1 ASIC in the CMOS 40 nm process. The chip is dedicated to high count rate single photon counting operation at the European Synchrotron Radiation Facility with Extremely Brilliant Source. The core of the prototype IC is the matrix of 64 32 pixels of 50 μm pitch. Each pixel contains a Charge Sensitive Amplifier (CSA) with a fast discharge block and a detector leakage current compensation circuit. The CSA is connected to a set of three discriminators. The readout channel is equipped with additional circuits, which provide different pulse pile-up compensation methods. The priority of the analog front-end electronics is to process the input signal in a short time (the CSA output pulse time width is only 18 ns) and to keep low noise (the equivalent noise charge at the level of 188 el. rms) with a power consumption equals to 26 μW/pixel. The chip is optimized for operation with a monochromatic X-ray beam with an energy of up to 30 keV. The measurements prove the possibility of counting up to 11.5 Gcps/mm2 based on a 10% dead time loss input rate parameter.

A Pixel Circuit With Leakage Current Compensation Using PWM-Based Data Cycling for AMLED Displays

This brief presents a leakage current compensation scheme by using a data cycling function to a pixel driver circuitry of the active-matrix light emitting diode (AMLED) displays. The proposed function cycles the stored dimming data to repeat pulse width modulation (PWM) multiple times at a given frame time. It compensates for a decay of the LED driving current due to leakage by repeatedly charging the target dimming data across a storage capacitor in the current driver. The proposed circuit has been fabricated using a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol{\mu }\text{m}$ </tex-math></inline-formula> CMOS process. The test chip includes a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\,\,\mathbf {\times }\,\,16$ </tex-math></inline-formula> pixel circuit array with a control system. The functional operation has been verified at a prototype using an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\,\,\mathbf {\times }\,\,16$ </tex-math></inline-formula> LED array system.

Small pixel high-spatial resolution photon-counting prototype IC for synchrotron applications

This paper presents the design and simulation of a prototype chip in the CMOS 40 nm process for high spatial resolution operation at the ESRF-EBS synchrotron. The core of the prototype IC is the pixel matrix with 50 µm pitch, operating in a single photon counting mode. Each pixel contains a Charge Sensitive Amplifier (CSA) with a fast discharge block and detector leakage current compensation circuit. The CSA output is directly connected to the discriminator with an offset trimming capability. The chip is optimized for operation with a monochromatic X-ray beam with an energy of up to 30 keV. Furthermore, several algorithms of interpixel communication are implemented in the chip to increase detector spatial resolution by using the charge sharing effect.

Design and Research of Protection and Action Characteristic Test Device

Before and after the EMC immunity test, it is necessary to verify whether the main performance indicators of the tested equipment are reduced. The protection and action characteristics test device is the equipment to verify the main performance indicators of mining electrical switches and motors. Its research and development involves a variety of equipment to cooperate to realize its system functions. However, there is no single manufacturer in the market to produce such equipment or system, which needs independent research and development according to the needs of the electrical equipment tested in the laboratory. The protection and action characteristic test device is applied to the mechanical characteristic test of high-voltage switch. It can be used as the test equipment for high-voltage and low-voltage leakage action value and time test, as well as the leakage current and capacitive current compensation efficiency test. It can also be used for the characteristic test of the test device, overcurrent protection characteristic test and other test items.

A PVT power immune compact 65 nm CMOS CSP design with a leakage current compensation feedback for CdZnTe/CdTe sensors dedicated to PET applications

SummaryPower consumption and image resolution are the major concerned while designing modern readout integrated circuits (ROICs) of Cadmium‐Telluride (CdTe)/Cadmium‐Zinc‐Telluride (CdZnTe) sensors for nuclear magnetic resonance imaging (MRI) and positron emission tomography (PET) applications. The key ROIC element, namely, preamplifier, must be monolithically integrated to the sensor chip and should guarantee low noise, low power, and high linearity along with assuring higher conversion gain and less chip area. A power immune, linear charge sensitive preamplifier (CSP) with a custom leakage current compensation feedback for (CdTe)/CdZnTe sensors is designed. A maximum power consumption of 120 μW, stable against process voltage and temperature (PVT) variations, is achieved. The compensation module cancels out current noise generated at the output of the circuit, lowering the power spectral density of about 84.26% than that of similar architectures, thus improving the signal‐to‐noise ratio (SNR) at the CSP output by a factor of 6.31. In turns, it injects about 100 pA of input direct‐current (DC) current and compensates the sensor leakage current therefore. Two input dynamics of (0.25–10) and (10.01–20)fC are achieved, providing two conversion factors of 23.06 and 19.00 mV/fC with 2.4% and 0.58% nonlinearity errors, respectively, using 1 pF sensor capacitance. Noise performance of the circuit is improved with 47.5 e‐rms and 62.46e−rms of equivalent noise charge (ENC) depending upon the input dynamic. The design is validated by Monte Carlo simulations and PVT analysis implemented in 65 nm complementary metal‐oxide semiconductor (CMOS) process, assuring a chip area of only 0.000246 mm2.

All-programmable low noise readout ASIC for silicon strip sensors in tracking detectors

The Programmable Read-out with Improved Noise-performance Charge Sensitive Amplifier (PRINCSA) is a prototype Application Specific Integrated Circuit (ASIC) designed for read-out of the silicon micro-strip sensors in the tracking detectors for Physics experiments. The main aim of this project was to minimize the overall system noise (Equivalent Noise Charge, ENC) and implement a range of programmable features to adjust the noise performance to varying conditions. The chip comprises three single-ended and three pseudo-differential channels that additionally allow for power supply interference reduction. All channels include a charge sensitive amplifier (CSA), a fast shaping amplifier for time measurements, and a slow shaping amplifier for amplitude measurements. The slow shaper’s architecture (in all channels) and its peaking time (in the single-ended channels) are configurable to test the capability of noise filtering for various dominant noise contributions (unipolar semi-Gaussian and complex conjugate poles filters). To further improve the power supply rejection ratio, additional on-chip filtering of the preamplifier biasing potential is included in every channel. For faster CSA baseline restoration, its feedback in all channels is equipped with a pulsed reset circuit. In this design, it is combined with a double-polarity Krummenacher circuit for leakage current compensation for both polarities of charge pulse and leakage current without compromising the large value of the CSA feedback resistance. The ASIC comprises a calibration circuit working in two operational modes: a standard double-polarity charge injection and a single-polarity charge injection (fast leading and slow falling edges of the calibration pulses) with programmable amplitude. The IC was fabricated in Q4 2018 using UMC CMOS 180 nm technology node.

A charge balancing technique for neurostimulators

A charge balancing technique that is applicable to dual-edge current nerve stimulators is proposed herein, which is primarily directed to achieving charge balance by controlling discharge times. Compared to the charge balancing technique proposed in other papers, the number of single-cycle imbalanced charges is less than 15 pC. In order to reduce the amount of imbalanced charge, indirect shunt technology, leakage current compensation technology and offset voltage compensation technology was proposed in this paper to build up a synchronization system. To ensure that the neural stimulator can still be in charge balance after performing multiple stimulation cycles, a short pulse insertion technique is applied to the circuit. The circuit was designed based on the TSMC 180 nm process and verified its functionality under the Cadence platform.

Input bias current reduction technique for operational amplifier in a standard CMOS technology

AbstractThis paper presents input bias current (Ibias) reduction technique for high impedance CMOS op‐amps with the proposed current compensation circuit to deal with the leakage current caused by Electro‐Static Discharge (ESD) protection circuit of the IC. High input impedance CMOS op‐amps are widely used for the application of high precision sensors with quite small input current. However, the leakage current of ESD protection circuit for op‐amp causes a nonideality error of the Ibias. Especially, the ESD leakage current increases drastically at the high temperature environment, and hence the Ibias of CMOS op‐amp also increased significantly. An ESD leakage current compensation circuit is introduced to reduce the Ibias of CMOS op‐amp. The prototype amplifier with the proposed current compensation circuit is designed and fabricated in standard 0.7 µm CMOS technology. Measurement results show that the Ibias is reduced to a 100 pA or less from a typical 2.3 nA at 150°C.

Prototype single-ended and pseudo-differential charge processing circuit for micro-strip silicon and gaseous sensors read-out

Detector read-out electronics for Physics Experiments as for example Compressed Baryonic Matter experiment at FAIR, Darmstadt, Germany, should meet tight requirements concerning noise (ENC < 1000 e− rms to guarantee event reconstruction), power consumption (< 10 mW/channel) and average input hit frequency of 250 kHit/s/channel. The ICs design should take into account not only the charge processing parameters but also the impact of the environmental and system-level conditions like radiation, noisy power supply, and temperature to ensure reliable and stable operation during an experiment in a system built with tens of thousands of devices. The operation with gaseous detectors requires particularly effective protection of the inputs against electrostatic discharge. The ESD protection circuit (in particular based on MOS transistors), together with the sensor itself, or AC-coupling capacitors (after irradiation) can be however a source of additional leakage current flowing into the first stage of charge processing chain and affecting the performance. The read-out electronics (in particular first stage—charge sensitive amplifier, CSA) and detector-related noise can be mitigated using proper filtration and signal shaping. However, noise introduced by external sources, like power supply interference, can not be limited only via proper shaping and filtration. When LC filtering is not possible (due to high magnetic fields), it may be beneficial to use differential or pseudo-differential signal processing. The purpose of this work was to test several ideas to improve noise performance and to make the architecture of charge processing chain configurable to better adapt to different target radiation imaging applications. The ASIC comprises four single-ended and four pseudo-differential signal processing channels. In both types of channels configurable slow shaper configuration is used—it is switchable CR-RC2 type shaper and complex conjugate poles 3rd order shaper. CSA feedback in single-ended architecture can be selected between MOS transistor working in a linear region and double-polarity Krummenacher circuit for leakage current compensation capability. The chip was designed and fabricated in Q4 2018 using 180 nm process. Front-end single-ended and differential channels occupy the area from 950 × 60 μm2 up to 1150 × 125 μm2 and consume 5 mW up to 12 mW of power respectively. The work presents design and measurements results.

A Low-Power Low-Distortion 20-GS/s Flash Analog-to-Digital Converter for Coherent Optical Receiver in 0.13-μm SiGe BiCMOS

High-speed, low-power analog-to-digital converter (ADC) is a critical element for 5-GBd, 20-Gb/s digital signal processing (DSP)-based coherent optical communication receiver. To satisfy high data transmission rate requirement of optical receiver, a single-core and open-loop flash ADC with a new proposed multiplexer-based encoder is presented in this paper. Compared with conventional encoder topology, the new proposed topology achieves the fastest encoding speed and lowest power consumption. The optimized distortion is achieved by utilizing a leakage current compensation technique and a local negative feedback method in switched-buffer track-and-hold amplifier (THA). Strict synchronization is obtained for clock signals by careful designing of layout in tree-based clock networks. Furthermore, a master–slave comparator incorporated with a preamplifier reduces signal-dependent kickback noise as well as offset voltage. By using master–slave comparators and proposed encoders, the sampling rate is up to 21.12[Formula: see text]GS/s. The 4-bit, 20-GS/s flash ADC is realized in 0.13-[Formula: see text]m SiGe BiCMOS technology and it only occupies 1.05[Formula: see text]mm[Formula: see text][Formula: see text][Formula: see text]1.46[Formula: see text]mm chip area. With a power consumption of 1.831[Formula: see text]W from 4-V supply, the ADC achieves an effective number of bits (ENOB) of 2.5 at 15[Formula: see text]GS/s.

Design of a fA wide dynamic range ADC for current sensing

Current sensing is important in various applications. The Utopia 2 Application Specific Integrated Circuit (ASIC) was developed in AMS 0.35 $$\upmu \hbox {m}$$ technology for radiation monitoring based on ionization chambers. The ASIC is able to measure current equal to 1 femtoampere (fA) after active leakage current compensation. The compensation is achieved with a second dummy compensating channel that is matched to the measuring channel. The ASIC was also designed to cope with input currents that span over nine decades of dynamic range. The analog to digital conversion is performed with charge balancing and counting. The maximum current that is equal to 5 $$\upmu \hbox {A}$$ can be measured after the introduction of a second range. The system has been characterized at a certified laboratory and is able to sense currents from 1 fA up to 5 $$\upmu \hbox {A}$$ .

Leakage current-induced effects in the silicon microstrip and gas electron multiplier readout chain and their compensation method

Leakage current flowing into the charge sensitive amplifier (CSA) is a common issue in many radiation detection systems as it can increase overall system noise, shift a DC baseline or even lead a recording channel to instability. The commonly known leakage current contributor is a detector, however other system components like wires or an input protection circuit may become a serious problem. Compensation of the leakage current resulting from the electrostatic discharge (ESD) protection circuit by properly sizing its components is possible only for a narrow temperature range. Moreover, the leakage current from external sources can be significantly larger. Many applications, especially High Energy Physics (HEP) experiments, require a fast baseline restoration for high input hit rates by applying either a low-value feedback resistor or a high feedback resistance combined with a pulsed reset circuit. Leakage current flowing in the feedback in conjunction with a large feedback resistance supplied with a pulsed reset results in a significant voltage offset between the CSA input and output which can cause problems (e.g. fake hits or instability). This paper shows an issue referred to the leakage current of the ESD protection circuit flowing into the input amplifier. The following analysis and proposed solution is a result of the time and energy readout ASIC project realization for the Compressed Baryonic Matter (CBM) experiment at FAIR (Facility for Antiproton and Ion Research) in Darmstadt, Germany. This chip is purposed to work with microstrip and gaseous detectors, with high average input pulses frequencies (250 kHit/s per channel) and the possibility to process input charge of both polarities. We present measurements of the test structure fabricated in UMC 180 nm technology and propose a solution addressing leakage current related issues. This work combines the leakage current compensation capabilities at the CSA level with high, controllable value of the amplifier feedback resistor independent of the leakage current level and polarity. The simulation results of the double, switchable, Krummenacher circuit-based feedback application in the CSA with a pulsed reset functionality are presented.

Utopia: A Nine Decade Femtoampere Sensitivity Current Digitizer and its Application in Ionizing Radiation Monitoring

Radiation measurements and monitoring are very important for particle physics accelerators, hadron therapy institutes, and nuclear facilities. An Application Specific Integrated Circuit (ASIC) able to digitize current generated from ionization chambers was designed and characterized in order to be used as the front-end of the new radiation monitoring system at CERN. The design of the Utopia 2 ASIC was motivated by the need to measure input currents as low as 2 fA and over a wide dynamic range of 9 decades. This paper presents the challenges, the design procedure, the architecture, and the measurement results of the front-end that was fabricated in AMS 0.35- $\mu \text{m}$ technology. The main limitation was related to the leakage currents that are injected into the input of the ASIC from various sources and are added to the signal of the detector. By active leakage current compensation, the ASIC can measure current down to 1 fA, and by introducing a multiple range architecture, the ASIC can digitize current up to $5~\mu \text{A}$ .

Design of analog pixels front-end active feedback

The paper presents the design of the active feedback used in a charge-sensitive amplifier. The predominant advantages of the presented circuit are its ability for setting wide range of pulse-time widths, small silicon area occupation and low power consumption. The feedback also allows sensor leakage current compensation and, thanks to an additional DC amplifier, it minimizes the output DC voltage variations, which is especially important in the DC coupled recording chain and for processes with limited supply voltage. The paper provides feedback description and its operation principle. The proposed circuit was designed in the CMOS 130nm technology.

Charge sharing write driver and half‐ pre‐charge 8T SRAM with virtual ground for low‐power write and read operation

A novel write bitline (BL) charge sharing write driver (CSWD) and a half-V DD read BL (RBL) pre-charge scheme is presented for a single-ended 8T static random access memory (SRAM). Before write enable (WE) signal assertion, CSWD equalises the write BLs by allowing their charge sharing. Both write BLs are equalised at the middle value of supply voltage using leakage current compensation block. Afterwards, as WE signal is asserted, CSWD produces the rail-to-rail levels at write BL pair. Charging of a BL from half-V DD to V DD essentially reduces the write dynamic power dissipation by 50%. Half-V DD precharging is used for RBL to achieve low-power read operation. Read port is powered by virtual ground rail to improve the RBL leakages. The authors compare the proposed 8T design (P8T) with conventional 6T (C6T) and 8T (C8T) designs in a 45 nm technology node. Write power dissipation is reduced by 42% and dynamic read power is reduced by more than 39%. Overall leakages are reduced by more than 18% compared with C6T and I on /I off ratio of the RBL is improved by more than two orders of magnitude compared with conventional 8T (C8T).

High-temperature characterisation and analysis of leakage-current-compensated, low-power bandgap temperature\xa0sensors

This paper analyses leakage current compensation techniques for low-power, bandgap temperature sensors. Experiments are conducted for circuits that compensate for collector-substrate, collector-base, body-drain and source-body leakage currents in a Brokaw bandgap sensor. The sensors are characterised and their failure modes are analysed at temperatures from 60 to 230^{,circ }hbox {C}. It is found that the most appropriate compensation circuit depends on the accuracy requirements of the application and on whether a stable reference voltage is required by other parts of the circuit. Experiments show that the power consumption is dominated by leakage current at high temperatures. One type of sensor was seen to consume 260 nW at 60 ^{,circ }hbox {C}, 2.1, upmu hbox {W} at 200^{,circ }hbox {C} and 14, upmu hbox {W} at 230^{,circ }hbox {C}. This work is motivated by the need to accurately monitor the temperature of power semiconductors in order to predict emerging faults in power semiconductor modules, a task for which cheap, single-chip, low-power, high-temperature, wireless bandgap temperature sensors are appropriate.