Leakage Current Compensation Research Articles

2 × VDD output buffer with 36.4% slew rate improvement using leakage current compensation

A 2 × VDD output buffer using leakage current compensation is demonstrated. With the proposed leakage current compensation circuit, the SR (slew rate) is improved 36.4-101.89% based on on-silicon measurement results given different VDDIO (1.0/1.2/1.8 V) and temperatures (from 0 to 100°C). The data rate is 510/630/400 MHz for VDDIO at 1.8/1.2/1.0 V, respectively. Moreover, the reliability problem, the gate oxide overstress and the hot carrier degradation is avoided. The proposed design is implemented using a typical 90 nm CMOS process. The active area is 0.425 × 0.0563 mm. The SR is measured in the range from 0.766 to 2.585 V/ns.

A Leakage Compensation Design for Low Supply Voltage SRAM

A leakage current compensation design for nanoscale SRAMs is proposed in this paper. The proposed compensation design is composed of a leakage current sensor, which generates a warning signal if the leakage is over a predefined threshold, and a compensation circuit following the sensor, which will be activated to speed up the read operation. At 0.6 V system voltage, the proposed compensation design reduces 27.86% of the average power dissipation, and 54.88% of the read delay at the expense of 3.64% area overhead. The proposed Static Random-Access Memory is implemented using the TSMC 40-nm CMOS logic technology. The energy per access is measured to be 0.9411 pJ given a 600-mV power supply and a 54-MHz system clock rate.

A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process.

This paper presents a 4 × VDD neuro-stimulator in a 0.18- μm 1.8 V/3.3 V CMOS process. The self-adaption bias technique and stacked MOS configuration are used to prevent transistors from the electrical overstress and gate-oxide reliability issue. A high-voltage-tolerant level shifter with power-on protection is used to drive the neuro-stimulator The reliability measurement of up to 100 million periodic cycles with 3000- μA biphasic stimulations in 12-V power supply has verified that the proposed neuro-stimulator is robust. Precise charge balance is achieved by using a novel current memory cell with the dual calibration loops and leakage current compensation. The charge mismatch is down to 0.25% over all the stimulus current ranges (200-300 μA) The residual average dc current is less than 6.6 nA after shorting operation.

A low-noise 64-channel front-end readout ASIC for CdZnTe detectors aimed to hard X-ray imaging systems

In this paper, we report on the recent development of a 64-channel low-noise front-end readout ASIC for CdZnTe detectors aimed to hard X-ray imaging systems. The readout channel is comprised of a charge sensitive amplifier, a leakage current compensation circuit, a CR-RC shaper, two S–K filters, an inverse proportional amplifier, a peak-detect-and-hold circuit, a discriminator and trigger logic, a time sequence control circuit and a driving buffer. The readout ASIC is implemented in TSMC 0.35μm mixed-signal CMOS technology, the die size of the prototype chip is 2.7mm×8.0mm. The overall gain of the readout channel is 200mV/fC, the power consumption is less than 8 mW/channel, the linearity error is less than 1%, the inconsistency among the channels is less than 2.86%, and the equivalent noise charge of a typical channel is 66 e− at zero farad plus 14 e− per picofarad. By connecting this readout ASIC to an 8×8 pixel CdZnTe detector, we obtained an energy spectrum, the energy resolution of which is 4.5% at the 59.5keV line of 241Am source.

Significantly enhanced ferroelectricity and magnetic properties in (Sr0.5Ca0.5)TiO3-modified BiFeO3 ceramics

BiFeO3 multiferroic ceramics were modified by introducing (Sr0.5Ca0.5)TiO3 to form solid solutions. The single phase structure was easy to be obtained in Bi1−x(Sr0.5Ca0.5)xFe1−xTixO3 (x = 0.2, 0.25, 0.3, and 0.4) solid solutions. Rietveld refinement of X-ray diffraction data revealed a transition from rhombohedral R3c (x = 0.2, 0.25, and 0.3) to orthorhombic Pnma (x = 0.4). Current density-field (J-E) characteristics indicated that the leakage current density was reduced by three orders of magnitude in Bi1−x(Sr0.5Ca0.5)xFe1−xTixO3 ceramics. Both the ferroelectricity and magnetic properties were significantly enhanced in the present solid solutions. P-E hysteresis loop measurements with dynamic leakage current compensation methods showed the significantly enhanced ferroelectric properties for x = 0.25 and 0.3 and the paraelectric behavior for x = 0.4. The best ferromagnetic characteristics were achieved in the composition of x = 0.25, where the saturated M-H loop was determined with Mr = 34.8 emu/mol. The improvement of ferroelectricity was mainly due to the suppressed leakage current, and the enhanced magnetism originated from the partial substitution of Fe3+ by Ti4+, which destroyed its previous spiral structure to allow the appearance of a macroscopic magnetization.

A 130.7-$\hbox{mm}^{2}$ 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology

A 32-Gb ReRAM test chip has been developed in a 24-nm process, with a diode as the selection device and metal oxide as the switching element. The memory array is constructed with cross-point architecture to allow multiple memory layers stacked above the supporting circuitry and minimize the circuit area overhead. Die efficiency is further improved by sharing wordlines and bitlines between adjacent blocks. As the number of sense amplifiers under the memory array is limited, a pipelined array control scheme is adopted to compensate the performance impact while utilizing the fast switching time of ReRAM cells. With the chip current consumption being dominated by the array leakage and sensitive to array bias and operating conditions, a charge pump stage control scheme is introduced to dynamically adapt to the operating conditions for optimal power consumption. Smart Read during sensing and leakage current compensation scheme during programming are applied to the large-block architecture and achieve a chip density that is several orders of magnitude higher than prior ReRAM developments.

Sample‐and‐hold circuit with dynamic switch leakage compensation

For sample-and-hold (S/H) circuits operating at low sampling rate and high temperature, the switch leakage current is one of the major error sources. A S/H circuit with dynamic switch leakage compensation is presented. The proposed leakage current compensation circuit generates switch leakage replicas that track the actual leakages in the sampling switches. A bidirectional current steering circuit allows the switch leakage to be dynamically compensated with the leakage replicas. A prototype S/H circuit is fabricated in a 1 μm silicon-on-isolation CMOS technology. Measurement has shown the effectiveness of dynamic leakage current compensation up to 280°C with a maximum 75% leakage reduction.

Leakage current characterization and compensation for piezoelectric actuator with charge drive

In this paper, the effects of leakage current on piezoelectric actuators with charge drive are presented, and a method to compensate it is proposed. Considering a piezoelectric stack driven by a switched capacitor charge pump as an example, the leakage current was found to be dependent on the voltage applied on the actuator but had a negligible relationship with the driving routes. The nonlinear relationship between the leakage current and the voltage was investigated, and a feedback circuit based on the applied voltage of the actuator was used for compensation. Experimental results showed that a displacement drift rate of lower than 0.033nm/s could be achieved with an applied voltage from 0V to 60V, whereas the drift rate was as large as 0.9nm/s without compensation.

A Current Compensation Bitline Sense Amplifier

A new bitline sense amplifier (SA) for improving performance in the presence of current compensation is analyzed. The proposed scheme utilizes a new leakage current compensation circuit, resulting in a 42.9% reduction in the delay from bitline discharge to the date been read out. Thus, this is very important for higher performance application, especially under advanced technology process.

A true single-phase clocked flip-flop with leakage current compensation

A true single-phase clocked (TSPC) flip-flop, which compensates for the leakage current generated at dynamic nodes, is proposed to cover a wide operational frequency range in submicron CMOS processes. To implement the proposed TSPC flip-flop, three feedback circuits composed of a gated inverter (GI) are added to the conventional TSPC flip-flop. The GI is controlled by a clock and the internal signal of the conventional flip-flop, without an external control signal or a complementary clock signal. Furthermore, the strength ratio of the normal path to the feedback path does not need to be considered for the proposed TSPC flip-flop since the feedback circuit is only enabled when the dynamic node acquires a floating state. The proposed TSPC flip-flop is designed using a 1-poly 6-metal 65nm CMOS process with a 1V supply voltage. The simulation results show that the proposed TSPC flip-flop, which is optimized for normal operation at an operational frequency of 2GHz, exhibits an error-free operation at low operational frequencies such as 1MHz. The three added feedback circuits increase the power consumption by 8.8% as compared to that of the conventional TSPC flip-flop and occupy 12.28% of the proposed flip-flop.

Low-Noise Analog ASIC for Silicon and CdTe Sensors

We report on the recent development of a 32-channel low-noise analog front-end ASIC "KW03" for hard X-ray and gamma-ray detectors. The ASIC aims for the readout of strip or pixel (pad) detectors utilizing silicon and cadmium telluride (CdTe) as detector materials. Each readout channel includes a charge-sensitive amplifier, bandpass filters and a sample-and-hold circuit. It also includes a leakage current compensation and pole-zero cancellation circuits to meet the various detector requirements. The equivalent noise level of a typical channel reaches 89 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> @ 0 pF (rms) and shows an input-capacitance characteristic of 7.5 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> /pF between 0 pF and 10 pF with a power consumption of 3 mW per channel. We mounted the ASIC on a low-temperature co-fired ceramic (LTCC) package and evaluated the spectral performance by combining with a CdTe diode detector. As a result, the gamma-ray spectrum of radioactive source 241 Am was obtained with a good energy resolution of 2.23 keV (FWHM) for gamma rays of 59.5 keV at -20°C.

A Phase-Locked Loop With Background Leakage Current Compensation

A background compensation method is presented to compensate the leakage current of MOS capacitors for phase-locked loops (PLLs) in nanoscale CMOS technology. A leakage detection circuit is used to adjust a voltage-controlled current source to compensate the leakage current. This PLL has been fabricated in 65-nm CMOS technology. With the background leakage current compensation, the measured peak-to-peak and rms jitters of this PLL at 1 GHz are 36 and 4.54 ps, respectively. Its power consumption is 8.4 mW for a 1.2-V supply voltage.

Preparation, Microstructure, and Ferroelectric Properties of Bi3.25La0.75Ti3−xMxO12 (M = Mo, W, Nb, V) Ceramics

A modified citrate-gel method for the preparation of Bi3.25La0.75Ti3−xMxO12 (BLTMx, M = Mo, W, Nb, V) ferroelectric powder and ceramics is presented. The cosubstituent precursors used were ammonium metal citrate aqueous solutions, which were prepared using corresponding metal oxides as starting materials (V2O5, MoO3, and WO3). The intermediate, an amorphous carbonized precursor, was found to directly transform into crystalline Bi4Ti3O12 at a temperature as low as 450 °C. The profound effects of cosubstitutions on the texture, microstructure, and ferroelectric properties of the prepared ceramics were studied. The maximal remanent polarization obtained was 15.9, 15.9, 15.3, and 16.3 μC/cm2 (10 Hz, 300 kV/cm) for the BLTNb0.03, BLTV0.03, BLTMo0.025, and BLTW0.025 ceramics, respectively. Dynamic leakage current compensation indicates that no appreciable electric leakage current contributes to the measured hysteresis loops. For BLTW0.025 ceramics, the static leakage current density is below 1.0 μA/cm2 within a...

Electron Charge Noise Minimization in 130 nm CMOS Preamplifiers

In this paper we present the design aspects for low-power, low-noise CMOS charge sensitive preamplifier that uses a leakage current compensation circuit for use with radiation sensors. The preamplifier has unipolar response with the peaking time of about 45 ns and the gain about 115– 145 mV/ke. Equivalent noise charge (ENC) is less than 80 e, when the input charge is 1–20 ke and the sensors capacitance is equal to 30 fF. In this work we present the quality function of the charge sensitive preamplifier, which characterizes best the optimal input transistor width W , with respect to equivalent noise charge and to the power consumptions.

Counting and Integrating Readout for Direct Conversion X-ray Imaging: Concept, Realization and First Prototype Measurements

A novel signal processing concept for X-ray imaging with directly converting pixelated semiconductor sensors is presented. The novelty of this approach compared to existing concepts is the combination of charge integration and photon counting in every single pixel. Simultaneous operation of both signal processing chains extends the dynamic range beyond the limits of the individual schemes and allows determination of the mean photon energy. Medical applications such as X-ray computed tomography can benefit from this additional spectral information through improved contrast and the ability to determine the hardening of the tube spectrum due to attenuation by the scanned object. A prototype chip in 0.35-micrometer technology has been successfully tested. The pixel electronics are designed using a low-swing differential current mode logic. Key element is a configurable feedback circuit for the charge sensitive amplifier which provides continuous reset, leakage current compensation and replicates the input signal for the integrator. This paper will discuss measurement results of the prototype structures and give details on the circuit design

A 32nm and 0.9V CMOS Phase-Locked Loop with Leakage Current and Power Supply Noise Compensation

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32㎚ predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440㎒ output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40M~725㎒ with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

Focus on sensors

Focus on sensors

Dynamic leakage current compensation in ferroelectric thin-film capacitor structures

We report on a measurement procedure to separate ferroelectric switching current and dielectric displacement current from the leakage current in leaky ferroelectric thin-film capacitor structures. The ac current response is determined for two adjacent frequencies. Taking advantage of the different frequency dependencies of the ferroelectric switching current, dielectric displacement current and ohmic current, the hysteresis loop is calculated without performing a static leakage current measurement, which causes a high dc field stress to the sample. The applicability of the proposed measurement procedure is demonstrated on a Pt∕Pb(Zr,Ti)O3∕IrO2 ferroelectric capacitor revealing a high leakage current.

Improving the performance of the feedback charge capacitance–voltagemethod

The feedback charge capacitance–voltage method (FCM) (Mego 1986Rev. Sci. Instrum. 58 2798) is a pure time-domain technique originallyused for measuring the quasi-static capacitance of semiconductor devices.The method is based on processing the output of a charge-to-voltageconverter in response to a double-step (pulse) excitation of the device.Using a transient voltage processor comprising three gated integratorsconnected to a mixing unit, steady-state (leakage) current may be the sourceof severe experimental error in capacitance. First, there is a parasiticcharge during the pulse that causes an error in sampling the baselinewhile activating the first channel for an aperture of finite duration Δt.Second, any uncompensated leakage present after the pulse leads to acharge increment representing what is called conduction loss in thefrequency domain. Measures to be taken towards minimizing both errorsare provided, based on a simultaneous action of active leakage currentcompensation and second-order filtering. A simple hardware solution foroptimizing the dynamic range of the FCM under the leakage is provided. Anon-instrumental FCM error connected with the constant dielectric loss indiamond thin films, due to the anomalous kinetics j(t) ∝ t−1 ofthe transient current, is analysed. The latter causes inaccuracy in assessing theinstantaneous (geometrical) capacitance of diamond-based Schottky diodes. Aproper gating of the charge-to-voltage converter is suggested for removal of thepredicted error.

A low-noise, low-power CMOS SOI readout front-end for silicon detector leakage current compensation with capability

A low-noise, low-power CMOS semiconductor on insulator (SOI) readout front-end aiming at dc coupling to silicon radiation detectors is presented in this paper. It is able to compensate the leakage current of detectors within a wide range up to 10 /spl mu/A. While the presented solution does not significantly deteriorate the amplifier noise performance it complies with demands for low-noise readout system for silicon detectors. This front-end system includes a charge-sensitive amplifier, a semi-Gaussian CR-RC shaping amplifier and an output buffer. It has been simulated and implemented in a CMOS SOI-SIMOX process. For no leakage current, an input referred equivalent noise charge (ENC) of 426 electrons (rms) for 0 pF of detector capacitance with a noise slope of 40 electrons/pF, a peaking time of 50 ns, and a conversion gain of 23.4 mV/fC have been obtained.