Abstract
This paper presents the design and simulation of a prototype chip in the CMOS 40 nm process for high spatial resolution operation at the ESRF-EBS synchrotron. The core of the prototype IC is the pixel matrix with 50 µm pitch, operating in a single photon counting mode. Each pixel contains a Charge Sensitive Amplifier (CSA) with a fast discharge block and detector leakage current compensation circuit. The CSA output is directly connected to the discriminator with an offset trimming capability. The chip is optimized for operation with a monochromatic X-ray beam with an energy of up to 30 keV. Furthermore, several algorithms of interpixel communication are implemented in the chip to increase detector spatial resolution by using the charge sharing effect.
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