Inductor Layout Research Articles

Integrated Inductor Layout Optimization for Synthesis of Microwave LC-Filters in Si/SiGe/GaAs Systems on a Chip

The paper proposes models of planar symmetric octagonal inductors that differ in the method of inductance calculating and consideration of the structure and characteristics of the technological process. The equations in a closed form for calculating models of integral planar inductors of various configurations are derived. The models were verified by comparing the frequency response of the developed 14-18 GHz bandpass filter model with the frequency response of experimental samples produced in the SiGe 130 nm process. The AFC of the produced filter samples is in the range of the developed filter model AFCs at the extreme points of the manufacturing tolerance. The developed algorithm of optimization for integral planar inductors layouts according to the criterion of maximum quality factor at the required frequency is presented. The use of the developed algorithm for integral planar inductors layouts optimization makes it possible to synthesize integrated LC-filters in Si, SiGe and GaAs technological processes with minimal passband losses and maximum gain slopes. The optimization algorithm is implemented as the program in the MathCad software. The optimal inductor layout calculation according to the criterion of maximum quality factor in the program takes tens of seconds a few minutes depending on the technological process structure complexity.

Integrated Inductor Model Verification for Microwave LC-filters in Si and SiGe Systems on a Chip

In this paper, the conductor model that can be used to design of various inductor layout configurations for any Si and SiGe technological processes is considered. The experimental prototypes of the test inductors were produced in the standard SiGe BiCMOS 130 nm process to verify the model. The chips measuring results showed that the characteristics of the prototypes taking into account the manufacturing tolerance are in the range of model simulated values. It has been found that the proposed model has a better convergence with the prototypes characteristics than 3D modeling. The equivalent circuit simulation speed can be orders of magnitude higher than the 3D simulation speed. The proposed model accuracy is achieved by taking into account the skin-effect and edge-effects in the dielectric and substrate. Using the skin-effect equivalent circuit the model can be run in Cadence Specter Simulator. It is necessary for the microwave LC-filters development.

Gyrator-C-Based CMOS Active Inductors: Analysis of Performance Optimization Techniques

Inductors are critical components in RF applications, such as filters, oscillators, and amplifiers. However, integrated spiral inductors on silicon (Si) have shown performance limitations. They do not meet the challenges of current trends toward miniaturized, low-cost, and on-chip multistandard communication systems [1]. While they have good performance in terms of noise, linearity, and power consumption, as they do not need a dc bias to work, electromagnetic interference with neighboring circuitry is a major problem associated with the layout of spiral inductors.

Skin Effect-Related AC Resistance Study in Macroscopic Scale Carbon Nanotube Yarn Applicable to High-Power Converter

This paper presents a study on the skin effect-related AC resistance of macroscopic scale carbon nanotube (CNT) yarn. The range of interest frequency in this study is up to 10 MHz which is considered conventional high-frequency power converters operating range. AC resistance of both CNT yarn and copper (Cu) wires are measured by impedance analyzer for the small-signal frequency-response. The 1-turn core-less layout of inductors made of both CNT yarn and Cu wire are implemented to eliminate the proximity effect and magnetic core. The measurement results are compared with the theoretical model results based on Bessel-Kelvin function. The results show that the increasing rate of AC resistance in CNT yarn is lower than in Cu wire as frequency increases so that it causes lower CNT yarn resistance at higher frequencies. It was found that the Cu wire measurement result follows the theoretical model whereas CNT yarn does not. Therefore, a new skin effect related AC resistance correction factor for CNT yarn is introduced. To verify the same trends in large signal level of current, conduction losses for both CNT yarn and Cu wire are tested as an inductor component in a power converter circuit working like a large signal generator. The losses were collected and presented for the same frequency range (between 1 and 10 MHz). The results show less losses with CNT yarn inductor. Finally, another CNT yarn-based inductor was constructed and tested in around 200 W power converter circuit. The results show 91.72% of high efficiency at 3.125 MHz switching frequency. The study shows that, for power converter circuits working in the range higher than 1 MHz, the CNT yarns are reasonable to replace Cu wires due to the lower skin effect- related losses.

Layout optimization of planar inductors for high-efficiency integrated power converters

The performance of dc–dc power converters is critically dependent on the inductors at their core. Planar spiral inductors are compact constructions that can be scaled and integrated without the limitations of traditional wire-wound devices. Therefore, they are increasingly employed to meet the needs of modern low-power applications, especially where size, weight and manufacturing costs are deciding factors. As a planar inductor is designed to fit the parameters of an application, it is paramount to take into account the associated parasitic effects that have an impact on the converter performance. This paper analyzes how the conversion efficiency of boost and buck integrated power converters depends on the parasitics elements of planar inductors, and how it can be improved by optimizing the inductor layout. In particular, the paper provides the guidelines for maximizing the time constant of the inductor by considering the different geometrical features that define the inductor shape. The trade-offs that maximize the inductance time constant for different shapes are introduced, and an algorithm is developed to optimize the performance with no area overhead. Finally, three boost converters are designed, simulated, and compared in a 65-nm CMOS technology to demonstrate the validity of the proposed approach, and the corresponding conversion efficiency improvement is assessed.

Characterization of a Planar Honeycomb-Based Inductor on Crosstalk/EMI Suppression

This paper presents a new planar inductor layout topology in honeycomb shape for crosstalk/electromagnetic interference (EMI) suppression. The proposed honeycomb-based (H-based) inductor uses six twisted subcoils having antiphase magnetic dipoles in staggered arrangement. The opposite directional magnetic dipoles result in a cancellation of interference emission to a nearby device. On the other hand, the interference emission from the nearby devices to the proposed H-based inductor can also be suppressed due to the twisted subcoils. In this study, the H-based inductor and the related testkeys implemented in TSMC 0.18 μ m CMOS technology are designed and characterized. The crosstalk/interference suppression capability of the H-based inductor to the nearby testing inductor can be improved by around 15–30 dB as compared with the conventional single-turn spiral inductor, when the operation frequency is 2.3 GHz and even the edge-to-edge spacing between the inductors approaches to 10 μ m.

Design and Optimization of Inductive-Coupling Links for 3-D-ICs

Recent research in the field of 3-D system integration has looked to the use of inductive-coupling links (ICLs) to provide vertical connectivity without incurring the inflated fabrication and testing costs associated with through-silicon vias. For power-efficient ICL design, optimization of the utilized physical inductor geometries is essential, but currently must be performed manually in a process that can take several hours. As a result, the generation of optimized inductor designs poses a significant challenge. In this paper, we address this challenge in three main contributions: 1) a novel, nonuniform planar inductor layout that exhibits enhanced performance when compared with conventional uniform inductors; 2) a rapid solver for evaluating inductor layouts; and 3) a high-speed optimization algorithm for determining best performing coil pairs. These three contributions are combined as a CAD tool for optimization of ICLs for 3-D-ICs (COIL-3-D). Results demonstrate that COIL-3-D achieves an average accuracy within 7.8% of finite-element tools consuming a small fraction of the time ( $1.5\times 10^{-3}$ %), significantly ameliorating the design of ICL-based 3-D-ICs. We also demonstrate that using COIL-3-D to optimize ICL inductor layouts can yield significant performance (up to 41.5% bandwidth improvement) and power (up to 8.1% power improvement) benefits, when compared with layouts used in prior ICL implementations. For these reasons, this paper unlocks new potential for low-cost, power-efficient 3-D integration using ICLs.

Micro-Fabricated Resonator Based on Inscribing a Meandered-Line Coupling Capacitor in an Air-Bridged Circular Spiral Inductor.

This letter presents a high-performance micro-fabricated resonator based on inscribing a meandered-line square coupling capacitor in an air-bridged circular spiral inductor on the GaAs-integrated passive device (IPD) technology. The main advantages of the proposed method, which inserts a highly effective coupling capacitor between the two halves of a circular spiral inductor, are the miniaturized size, enhanced coupling coefficient, and improved selectivity. Moreover, using an air-bridge structure utilizes the enhanced mutual inductance in which it maximizes the self-inductance by a stacking inductor layout to obtain a high coupling effect. The simulated and measured S-parameters of a prototype resonator with an effective overall circuit size of 1000 µm × 800 µm are in good agreement. The measured insertion and return losses of 0.41 and 24.21 dB, respectively, at a measured central frequency of 1.627 GHz, as well as an upper band transmission zero with a suppression level of 38.7 dB, indicate the excellent selectivity of the developed resonator.

Design and analysis of a novel MEMS spiral inductor with high quality factor

In this paper a novel spiral inductor with high quality (Q)-factor is presented. Non-uniform current density distribution, especially in inner turn, increases the effective metal resistance due to skin and proximity effect. In order to overcome this problem, an improved inductor layout with non-uniform metal width and non-uniform spacing is proposed to increase the quality factor. For this inductor layout, from outer coil to inner coil, the metal widths are reduced but spacing between strips are increased. Mainly due to the decrease of eddy current loss by weakening the current crowding effect in the center of the spiral inductor. By reducing the current crowding effect, the effective resistance is minimized, thereby increase the quality factor. Simulation has been taken using COMSOL Multiphysics software. The results indicate that maximum value of quality factor and self-inductance of the novel inductor have been obtained about 80.34 and 324 nH, respectively. Which Q-factor improves 27% more than conventional inductors with uniform width. The dimension of the inductor is 1700 × 1660 μm.

Efficient optimization of fully-integrated inductive DC–DC converters comprising tapered inductor layout synthesis and temperature effects

The evolution of computer-aided design tools has extended the capabilities of a designer by pushing the optimality of complex circuits beyond the ad hoc manual implementation. This work presents a framework to co-optimize the circuit and the layout parameters of fully integrated inductive DC–DC converters. The framework comprises expensive optimization that is speeded up by active learning sample selection and evolutionary techniques to acquire an optimal converter. A tapered inductor topology is used to increase the quality of the on-chip inductor and to improve the efficiency of the overall monolithic DC–DC converter. The optimization framework is validated by co-optimizing the design parameters and the tapered inductor layout for a fully-integrated DC–DC boost converter in a 0.13 μm CMOS technology. The power loss in the circuit is reduced with 27 % resulting in a 7 % efficiency improvement, compared to a fully-integrated DC–DC boost converter with a regular inductor topology.

A 1-mW 1.13–1.9 GHz CMOS LC VCO Using Shunt-Connected Switched-Coupled Inductors

A low-power wideband LC VCO has been designed and implemented in a 90-nm CMOS technology. Wide tuning range, low phase noise and low power consumption are achieved thanks to the adopted LC tank, which makes use of shunt-connected switched-coupled inductors and a proper arrangement of varactors. The shunt-connected switched-coupled inductors provide coarse tuning and phase noise optimization without using amplitude calibration loop or trimming of the bias current. The proposed varactors configuration employs accumulation mode thin and thick MOS devices, which has been differently biased to obtain tuning range maximization along with minimization of the amplitude-to-phase noise conversion. The LC-tank topology and inductor layout have been properly designed to attain a die area comparable to a single-inductor VCO, taking advantage of the inductors mutual coupling. The VCO exhibits a phase noise at 1-MHz offset frequency lower than -114 dBc/Hz over the entire tuning range and achieves -126.1 dBc/Hz at 1.2 GHz. It provides a tuning range of 51% from 1.13 GHz to 1.9 GHz with a tuning voltage ranging from 0 to 1.2 V. Despite a very low current consumption, which is 0.88 mA from a 1.2-V supply, the proposed VCO has the outstanding PFTN figure-of-merit of 10. The VCO core die area is 0.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Improving the quality factor of an RF spiral inductor with non-uniform metal width and non-uniform coil spacing

An improved inductor layout with non-uniform metal width and non-uniform spacing is proposed to increase the quality factor (Q factor). For this inductor layout, from outer coil to inner coil, the metal width is reduced by an arithmetic-progression step, while the metal spacing is increased by a geometric-progression step. An improved layout with variable width and changed spacing is of benefit to the Q factor of RF spiral inductor improvement (approximately 42.86%), mainly due to the suppression of eddy-current loss by weakening the current crowding effect in the center of the spiral inductor. In order to increase the Q factor further, for the novel inductor, a patterned ground shield is used with optimized layout together. The results indicate that, in the range of 0.5 to 16 GHz, the Q factor of the novel inductor is at an optimum, which improves by 67% more than conventional inductors with uniform geometry dimensions (equal width and equal spacing), is enhanced by nearly 23% more than a PGS inductor with uniform geometry dimensions, and improves by almost 20% more than an inductor with an improved layout.

LTCC Spiral Inductor Synthesis and Optimization With Measurement Verification

In RF/microwave circuit design, inductor design is one of the most difficult and time-consuming tasks due to the tedious trial-and-error optimization process to achieve the target specifications such as inductance, quality factor and occupied space. This paper brings forward a fast spiral inductor synthesis method, which automatically generates physical layout of inductors according to electrical specifications. By fusion of substrate-aware partial element equivalent circuit (PEEC) model with nonlinear optimization engine, our modeling and synthesis strategies have been verified with industrial field solver and measurement results. Our calculation results got less than 7% error for inductance and less than 9% for quality factor as compared to the results from full-wave electromagnetic simulation software. This can provide a fast and good initial inductor design for designer.

Analysis of Inductive Coupling and Design of Rectifier Circuit for Inter-Chip Wireless Power Link

A wireless power link utilizing inductive coupling is developed between stacked chips. In this paper, we discuss inductor layout optimization and rectifier circuit design. The inductive-coupling power link is analyzed using simple equivalent circuit models. On the basis of the analytic models, the inductor size is minimized for the given required power on the receiver chip. Two kinds of full-wave rectifiers are discussed and compared. Various low-power circuit design techniques for rectifiers are employed to decrease the substrate leakage current, reduce the possibility of latch-up, and improve the power transmission efficiency and the high-frequency performance of the rectifier block. Test chips are fabricated in a 0.18µm CMOS process. With a pair of 700 × 700µm2 on-chip inductors, the test chips achieve 10% peak efficiency and 36mW power transmission. Compared with the previous work the received power is 13 times larger for the same inductor size [7].

Chip-level integration of RF MEMS on-chip inductors using UV-LIGA technique

This paper presents a chip-level integration of radio-frequency (RF) microelectromechanical systems (MEMS) air-suspended circular spiral on-chip inductors onto MOSIS RF circuit chips of LNA and VCO using a multi-layer UV-LIGA technique including SU-8 UV lithography and copper electroplating. A high frequency simulation package, HFSS, was used to determine the layout of MEMS on-chip inductors with inductance values close to the target inductance values required for the RF circuit chips within the range of 10%. All MEMS on-chip inductors were successfully fabricated using a contrast enhancement method for 50 μm air suspension without any physical deformations. High frequency measurement and modeling of the integrated inductors revealed relatively high quality factors over 10 and self-resonant frequencies more than 15 GHz for a 1.44 nH source inductor and a 3.14 nH drain inductor on low resistivity silicon substrates (0.014 Ω cm). The post-IC integration of RF MEMS on-chip inductors onto RF circuit chips at a chip scale using a multi-layer UV-LIGA technique along with high frequency measurement and modeling demonstrated in this work will open up new avenues with the wider integration feasibility of MEMS on-chip inductors in RF applications for cost-effective prototype applications in small laboratories and businesses.

Coupling Effect of On-Chip Inductor With Variable Metal Width

This study proposes a proper layout of on-chip inductors to diminish the coupling effect in silicon-based technology. Keeping self inductance constant, the mutual inductance is measured to characterize coupling effect in three test keys. A layout with variable metal width of inductor is found to alleviate mutual inductance. Experiment results demonstrate the mutual inductance decreases 33.5% compared with standard layout. This information will be helpful in implementation of more than one inductor into radio frequency integrated circuits (RFICs).

위상 잡음을 개선한 CMOS VCO의 설계 및 제작

본 논문에서는 온-칩 스파이럴 인덕터 해석에 대한 3차원 전자장 시뮬레이션 방법을 제시하였으며, 이 방법은 정확히 예측 가능한 CMOS VCO를 설계하는데 적용될 수 있음을 보였다. VCO는 CMOS 0.25 um 표준 공정을 이용하여 LC-공진형으로 구현하였으며, 공진기의 스파이럴 인덕터는 실리콘 기판과의 사이에 그라운드 패턴을 삽입한 경우와 그렇지 않은 경우에 대해 각각 VCO를 구현하여 인덕터의 Q값 개선에 의해 VCO의 위상 잡음이 어느 정도 개선되는지를 검증하였다. 제작된 VCO는 2.5 V 제어 전압에서 3.094 GHz, -12.15 dBm 출력을 가지며, LC 공진에 사용된 단일 인덕터의 Q는 그라운드 패턴을 삽입한 경우 3 GHz에서 8% 정도 개선됨을 시뮬레이션을 통해 검증하였으며, 이로 인한 위상 잡음은 3 MHz 오프셋 주파수에서 9 dB 개선되어짐을 실험을 통해 확인하였다. In this paper, a 3-D EM simulation methodology for on-chip spiral inductor analysis has provided and it is shown that the methodology can be adapted to the highly predictable design for CMOS VCO. LC-resonator type VCO have fabricated by using standard 0.25 um CMOS process. And the LC VCO layout case which has pattern ground shielded inductors and the other layout case which has no pattern grounded inductors were fabricated for the verification of their effects on the VCO's phase noise by reducing the Q-factor of inductors. Fabricated VCO has 3.094 GHz, -12.15 dBm output at the tuning voltage of 2.5 V, and from the simulation, Q-factor of the pattern grounded inductor has increased 8% at 3 GHz, and from the measurement results, the phase noise has reduced by 9 dB at the 3 MHz off-set frequency for the pattern grounded inductor layout case.

Integrated inductors on porous silicon

AbstractWe examine porous Si as a thick RF‐isolation layer for on‐chip inductors and separate the loss sources that downgrade the Q factors into their material components, namely Si substrate loss and metal types common to standard CMOS technologies. First we validate theoretical designs with measurements in standard 0.18 μm CMOS technology. Then we examine the effect of a porous Si substrate on a fixed metal layout of a 2‐metal optimized inductor design compatible either with 0.18 μm CMOS technology using Aluminum or with 0.13 μm CMOS technology using Copper metallization. For typical on‐chip inductor layouts of (200–300 μm)2, we show that a 50 μm thick porous Si layer produces negligible current distributions inside the underlying lossy Si substrate, compared to the ones without it, which maintain high values throughout a large lateral extent of the die. In Al technology, a fixed inductor layout produces Q ‐factor enhancements of the order of 50%, compared to the case where no porous Si layer is used. In a 0.13 μm‐compatible CMOS technology using Cu on porous Si, the resulting Q ‐factors increase by a factor of 2 and reach values of 30 or more in the 3 GHz frequency range. For porous‐Si‐isolated inductors we compare the effect of metal losses and show that the resulting Q ‐factors scale with the metal conductivity. (© 2007 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect

A wireless bus for stacked chips was developed by utilizing inductive coupling among them. This paper discusses inductor layout optimization and transceiver circuit design. The inductive coupling is analyzed by a simple equivalent circuit model, parameters of which are extracted by a magnetic field model based on the Biot-Savart law. Given communication distance, transmit power, data rate, and SNR budget, inductor layout size is minimized. Two receiver circuits, signal sensitive and yet noise immune, are designed for inductive nonreturn-to-zero (NRZ) signaling where no signal is transmitted when data remains the same. A test chip was fabricated in 0.35-/spl mu/m CMOS technology. Accuracy of the models is verified. Bit-error rate is investigated for various inductor layouts and communication distance. The maximum data rate is 1.25 Gb/s/channel. Power dissipation is 43 mW in the transmitter and 2.6 mW in the receiver at 3.3 V. If chip thickness is reduced to 30 /spl mu/m in 90-nm device generation, power dissipation will be 1 mW/channel or bandwidth will be 1 Tb/s/mm/sup 2/.

A 10-GB/s SONET-compliant CMOS transceiver with low crosstalk and intrinsic jitter

A 4:1 SERDES IC suitable for SONET OC-192 and 10-Gb/s Ethernet is presented. The receiver, which consists of a limiting amplifier, a clock and data recovery unit, and a demultiplexer, locks automatically to all data rates in the range 9.95-10.7 Gb/s. At a bit error rate of less than 10/sup -12/, it has a sensitivity of 20 mV. The transmitter comprises a clock multiplying unit and a multiplexer. The jitter of the transmitted data signal is 0.2 ps RMS. This is facilitated by a novel notched inductor layout and a special power supply concept, which reduces cross-coupling between the transmitter and receiver. Integrated in a 0.13-/spl mu/m CMOS technology, the total power consumption from both 1.2- and 2.5-V supplies is less than 1 W.