Efficient optimization of fully-integrated inductive DC–DC converters comprising tapered inductor layout synthesis and temperature effects

Abstract

The evolution of computer-aided design tools has extended the capabilities of a designer by pushing the optimality of complex circuits beyond the ad hoc manual implementation. This work presents a framework to co-optimize the circuit and the layout parameters of fully integrated inductive DC–DC converters. The framework comprises expensive optimization that is speeded up by active learning sample selection and evolutionary techniques to acquire an optimal converter. A tapered inductor topology is used to increase the quality of the on-chip inductor and to improve the efficiency of the overall monolithic DC–DC converter. The optimization framework is validated by co-optimizing the design parameters and the tapered inductor layout for a fully-integrated DC–DC boost converter in a 0.13 μm CMOS technology. The power loss in the circuit is reduced with 27 % resulting in a 7 % efficiency improvement, compared to a fully-integrated DC–DC boost converter with a regular inductor topology.