Optimization of fully-integrated power converter circuits comprising tapered inductor layout and temperature effects

Abstract

A technique for the optimization of fully-integrated inductive DC-DC converters is presented. An optimization framework is used to acquire an optimal converter, focusing on the on-chip inductor as well as on the accurate layout-based modeling of temperature effects. For the inductor in inductive DC-DC converters, a tapered topology is introduced. A fully-integrated DC-DC boost converter is designed and optimized in a 0.13 µm CMOS technology. The power loss in the circuit is reduced with 27 % resulting in a 7 % efficiency improvement, compared to a fully-integrated DC-DC boost converter with a regular inductor topology.