Integrated inductors on porous silicon

Abstract

AbstractWe examine porous Si as a thick RF‐isolation layer for on‐chip inductors and separate the loss sources that downgrade the Q factors into their material components, namely Si substrate loss and metal types common to standard CMOS technologies. First we validate theoretical designs with measurements in standard 0.18 μm CMOS technology. Then we examine the effect of a porous Si substrate on a fixed metal layout of a 2‐metal optimized inductor design compatible either with 0.18 μm CMOS technology using Aluminum or with 0.13 μm CMOS technology using Copper metallization. For typical on‐chip inductor layouts of (200–300 μm)2, we show that a 50 μm thick porous Si layer produces negligible current distributions inside the underlying lossy Si substrate, compared to the ones without it, which maintain high values throughout a large lateral extent of the die. In Al technology, a fixed inductor layout produces Q ‐factor enhancements of the order of 50%, compared to the case where no porous Si layer is used. In a 0.13 μm‐compatible CMOS technology using Cu on porous Si, the resulting Q ‐factors increase by a factor of 2 and reach values of 30 or more in the 3 GHz frequency range. For porous‐Si‐isolated inductors we compare the effect of metal losses and show that the resulting Q ‐factors scale with the metal conductivity. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)