Device Layer Research Articles

Room-temperature spin-conserved electron transport to semiconductor quantum dots using a superlattice barrier.

To realize the optical transfer of electron spin information, developing a semiconductor layer for efficient transport of spin-polarized electrons to the active layers is necessary. In this study, electron spin transport from a GaAs/Al0.3Ga0.7As superlattice (SL) barrier to In0.5Ga0.5As quantum dots (QDs) is investigated at room temperature through a combination of time-resolved photoluminescence and rate equation analysis, separating the two transport processes from the GaAs layer around the QDs and SL barrier. The electron transport time in the SL increases for a thicker quantum well (QW) of SL due to the weaker wavefunction overlap between adjacent QWs. Additionally, the degree of conservation of spin polarization during transport varies with QW thickness. Rate equation analysis demonstrates an electron transport from SL to QDs while maintaining a high spin polarization for thick QWs. The achieved spin-conserved electron transport can be attributed to the combination of electron transport being sufficiently faster than the spin relaxation in SL and the suppressed spin relaxation in the p-doped GaAs layer capping the QDs. The findings indicate that SL is a promising candidate as an electron spin transport layer for optical spin devices.

Synthesis and Characterization of Functionalized Poly(9-vinylcarbazole) for light-emitting diode applications

Organic light-emitting diode (OLED) has been successfully applied to replace conventional lighting systems due to its ability to adjust color emission, low energy consumption, and high contrast ratio. One of the polymers of interest in this area is polyvinyl carbazole, PVK, given its characteristics, such as forming stable radicals, high thermal and photochemical stability, and high charge carrier mobility. The modification of PVK has contributed positively to its performance as an electroluminescent layer in the constitution of OLED devices, as seen in works carried out by Mota & Marques (2019); Brito & Marques (2020); Correia & Marques (2022); Geffroy & Grana (2019); Pachariyangkun & Suda (2020). The present study aimed to synthesize and functionalize poly(9-vinylcarbazole) as well as its characterization by thermoanalytical (TG, DTA and DSC) and spectroscopic (FTIR) techniques in order to verify the efficiency of the proposed synthesis. To date, no studies have been found in the literature using the compound 3-(4,4,5,5-Tetramethyl-[1,3,2]dioxaborolan-2-yl)-dibenzofuran in PVK for application in the emitting layer of optoelectronic devices.

Investigation of Epitaxial Misfit Strain Influence at the CsSn(I1-xBrx)3/SnO2 Interface on Photovoltaic Parameters in Cu2O/CsSn(I1-xBrx)3/SnO2 Perovskite Solar Cells

This work involves the numerical simulation of the photovoltaic performance of a single perovskite solar cell based on the Cu2O/CsSn(I1-xBrx)3/SnO2 structure, utilizing a lead-free inorganic perovskite absorber layer CsSn(I1-xBrx)3 with variable bromine content represented by the ratio x. The study aims to evaluate performance fluctuations due to misfit deformation effects at the interface between the SnO2 electron transport layer (ETL) and the absorber on photovoltaic parameters. The simulation model incorporates variations in the physical parameters of the device layers dependent on the ratio x. This enables the calculation of bandgap energy fluctuations according to strain theory and assesses the resultant impact on photovoltaic parameters due to strain at the SnO2/CsSn(I1-xBrx)3 interface. Performance results are presented as a function of bromine composition x, considering both the presence and absence of deformation effects. The study clearly demonstrates the significant impact of misfit deformation on bandgap energy fluctuation, emphasizing the need to optimize bromine content to balance deformation effects and achieve optimal performance. Specifically, the results show a maximum efficiency of 19.72% at x=0.56 for the undeformed structure, and 19.30% at x=0.50 for the deformed structure. This study refines simulation results and underscores the critical role of deformation engineering in modulating energy gaps.

Organic Solvent-Based PEDOT:PSS Solution for Air-Processed Organic Photovoltaics.

PSS is one of the best hole transport materials in organic photovoltaics (OPV). However, due to poor wettability, the aqueous PEDOT:PSS (a-PEDOT) is not applicable for inverted structured OPV as a hole transport layer (HTL) on top of the active layer. In this work, organic solvent-based PEDOT:PSS (o-PEDOT) with improved wettability was prepared by the solvent-replacement method through centrifugal ultrafiltration, dialysis membrane, and thermal evaporation. Adopting o-PEDOT as the HTL on the top surface of the active layer, the inverted OPVs were successfully prepared through a solution process. Importantly, due to good conductivity and suitable work function, the o-PEDOT can also act as the interconnection layer (ICL) in air-processed tandem OPV devices. The tandem device achieved a champion PCE of 15%, among the best reports of solution-processed homotandem OPV under open-air conditions. The flexible tandem OPV using o-PEDOT as an ICL was also demonstrated, with an efficiency of over 14%.

Spray pyrolysis–derived V2O5 thin films as an alternative electrochromic layer for electrochromic devices

In this study, vanadium oxide films were produced in the vanadium pentoxide (V2O5) films phase as an alternative electrochromic layer for electrochromic devices by ultrasonic spray pyrolysis technique at 300°C. The V2O5 films were subjected to heat treatment at different temperatures (400°C–450°C–500°C) and the ellipsometric, structural, morphological, optical, and electrical properties of the films were investigated. The optical parameters of the V2O5 films were calculated by different theoretical methods and compared with the ellipsometric results. The average thickness and refractive index values are 172 nm and 2.29, respectively. The V2O5 films showed high optical absorbance in the visible region and bandgap energy values ranged from 2.10 to 2.44 eV. The resistivity and roughness of the films decreased. The average roughness was determined to be 45 nm on average. These results suggest that V2O5 phase films, whose physical properties are improved by annealing without phase change, can be considered as promising electrochromic layers for electrochromic devices applications.

Investigation of solution-processed tungsten disulfide as switching layer in flexible resistive memory devices for performance and stability

Abstract Solution-processed tungsten disulfide (WS2) is demonstrated as a promising resistive switching layer for flexible resistive random access memory (RRAM) devices. For this study, WS2 nanoparticle solution was prepared by liquid exfoliation process from WS2 powder and comprehensive material investigation was performed to understand the suitability for device fabrication through morphologies and electronic behavior. Devices were fabricated on indium tin oxide (ITO) coated flexible polyethylene terephthalate (PET) with ITO acting as bottom electrode (BE) and silver (Ag) deposited as top electrode (TE) with thin film of WS2 prepared by spin coating as an active layer between electrodes. These fabricated flexible RRAM devices exhibited resistive switching characteristics with low operating voltages (V SET ∼0.5 V and V RESET ∼−1.4 V) over 100 consecutive cycles, along with impressive retention time of ∼104 s and high I ON/I OFF of ∼104. The performance variation of these devices was also investigated upon bending at radii of 12 mm and 5 mm indicating consistent switching, however a decay in LRS was observed after 250 s upon investigation of retention. These findings suggest that solution-processed thin films of WS2 nanomaterial can act as a promising switching layer for flexible electronics.

Nanometer Interlaced Displacement Metrology Using Diffractive Pancharatnam-Berry and Detour Phase Metasurfaces.

Resolving structural misalignments on the nanoscale is of utmost importance in areas such as semiconductor device manufacturing. Metaphotonics provides a powerful toolbox to efficiently transduce information on the nanoscale into measurable far-field observables. In this work, we propose and demonstrate a novel interlaced displacement sensing platform based on diffractive anisotropic metasurfaces combined with polarimetric Fourier microscopy capable of resolving a few nanometer displacements within a device layer. We show that the sensing mechanism relies on an interplay of Pancharatnam-Berry and detour phase shifts and argue how nanoscale displacements are transduced into specific polarization signatures in the diffraction orders. We discuss efficient measurement protocols suitable for high-speed metrology applications and lay out optimization strategies for maximal sensing responsivity. Finally, we show that the proposed platform is capable of resolving arbitrary two-dimensional displacements on a device.

Application of Solution-Processed High-Entropy Metal Oxide Dielectric Layers with High Dielectric Constant and Wide Bandgap in Thin-Film Transistors.

High-k metal oxides are gradually replacing the traditional SiO2 dielectric layer in the new generation of electronic devices. In this paper, we report the production of five-element high entropy metal oxides (HEMOs) dielectric films by solution method and analyzed the role of each metal oxide in the system by characterizing the film properties. On this basis, we found optimal combination of (AlGaTiYZr)Ox with the best dielectric properties, exhibiting a low leakage current of 1.2 × 10-8 A/cm2 @1 MV/cm and a high dielectric constant, while the film's visible transmittance is more than 90%. Based on the results of factor analysis, we increased the dielectric constant up to 52.74 by increasing the proportion of TiO2 in the HEMOs and maintained a large optical bandgap (>5 eV). We prepared thin film transistors (TFTs) based on an (AlGaTiYZr)Ox dielectric layer and an InGaZnOx (IGZO) active layer, and the devices exhibit a mobility of 18.2 cm2/Vs, a threshold voltage (Vth) of -0.203 V, and an subthreshold swing (SS) of 0.288 V/dec, along with a minimal hysteresis, which suggests a good prospect of applying HEMOs to TFTs. It can be seen that the HEMOs dielectric films prepared based on the solution method can combine the advantages of various high-k dielectrics to obtain better film properties. Moreover, HEMOs dielectric films have the advantages of simple processing, low-temperature preparation, and low cost, which are expected to be widely used as dielectric layers in new flexible, transparent, and high-performance electronic devices in the future.

A novel layered culture device reveals spatial dynamics of root element uptake and optimal silicon application site for mitigating chromium uptake by rice

Understanding root uptake mechanisms for various elements is crucial for optimizing heavy metal remediation strategies and enhancing plant-nutrient interactions. However, simple and effective methods to differentiate the contributions of specific root segments in element uptake are lacking. Here, we developed a layered culture device consisting of a culture box and a plant suspension mechanism, which isolates different root segments through solid media and waterproof coating. Then, we used the device to investigate the roles of distinct root segments (0–1 cm and 1–2 cm from the tip) in heavy metal chromium (Cr) and beneficial element silicon (Si) uptake in rice. The results indicated that the 0–1 cm root segment contributed approximately 58% of leaf Cr(VI), with higher efflux compared to the 1–2 cm segment. Conversely, the 1–2 cm root segment served as the primary source of leaf Si and Cr(III), accounting for 62% and 54%, respectively. The translocation factors for Cr(VI) were similar for both segments (0.039 and 0.032), while the Cr(III) translocation factor for the 0–1 cm root segment (0.061) was 2.8 times that of the 1–2 cm segment. Notably, Si application to the 0–1 cm segment most effectively alleviated Cr (III) and Cr (VI) stress, boosting shoot length, fresh weight, and chlorophyll concentration and reducing Cr concentrations in roots and leaves by 24.7%–65.7%. In contrast, Si application to the 1–2 cm segment had minimal impact on rice growth or Cr uptake. These results suggest a deep Si application strategy for remediating Cr-contaminated soil. The innovative device provides a scientific foundation for distinguishing element uptake contributions of different root segments and enhancing the utilization efficiency of remediation materials and nutrient management in agriculture.

Organic ferroelectric transistors with composite dielectric for efficient neural computing

Organic ferroelectric field-effect transistors (Fe-OFETs) exhibit exceptional capabilities in mimicking biological neural systems and represent one of the primary options for flexible artificial synaptic devices. Ferroelectric polymers, such as poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)), given their strong ferroelectricity and facile solution processing, have emerged as the preferred choices for the ferroelectric dielectric layer of wearable devices. However, the solution processed P(VDF-TrFE) films can lead to high interface roughness, prone to cause excessive gate leakage. Meanwhile, the ferroelectric layer in neural computing and memory applications also faces a trade-off between storage time and energy for read/write operations. This study introduces a composite dielectric layer for Fe-OFETs, fabricated via a solution-based process. Different thicknesses of poly(N-vinylcarbazole) (PVK) are shown to significantly alter the ferroelectric hysteresis window and leakage current. The optimized devices exhibit synaptic plasticity with a transient current of 3.52 mA and a response time of approximately 50 ns. The Fe-OFETs with the composite dielectric were modeled and integrated into convolutional neural networks, achieving a 92.95% accuracy rate. This highlights the composite dielectric's advantage in neuromorphic computing. The introduction of PVK optimizes the interface and balances device performance of Fe-OFETs for neuromorphic computing.

Approaches for white organic light-emitting diode via solution-processed blue and yellow TADF emitters: Charge balance and host-guest interactions in a single emission layer

[Display omitted] Although OLEDs are widely employed nowadays for display technology devices, their application for room-lighting illumination remains a challenge due to the cost-effectiveness issues, mainly related to device fabrication. In this sense, the present study investigates the optimization of blue-emitting TADF (DMOC-DPS) and yellow-emitting TADF (TXO-TPA) compounds in solution-processed OLEDs to achieve efficient white light emission in a two-organic layer device. Four different host materials were studied, aiming to balance the charge mobility of holes and electrons. The host materials used include (in %wt.) a 1:1 mixture of mCP and DPEPO (HOST1), a 3:2 mixture of PVK and DPEPO (HOST2), a 3:2 mixture of PVK and mCP (HOST3), and a 3:2 mixture of PVK and butyl-PBD (HOST4). The experimental results obtained from the solution-processed OLEDs indicate that DMOC-DPS is predominantly a hole transport material, and hosts with predominantly n-type character, such as HOST1 and HOST4, resulting in the most efficient white-OLEDs by the most balanced charge mobility. With structure optimization, WOLEDs achieved 6.43 % EQE with a brightness of 2621 cd/m2 (not integrated) and 6.06 % EQE with a brightness of 1986 cd/m2 for HOST4 and HOST1, respectively. The emission characteristics were influenced by host materials characteristics, with blue and yellow emissions being fine-tuned to produce complementary colors. This study highlights the critical role of charge mobility balance in the emissive layer and demonstrates the potential of independently optimizing blue and yellow TADF components for high-performance WOLEDs suitable for indoor lighting applications.

Ultra-sensitive and precisely decoupled pressure and temperature detection with a “soft-hard” asymmetrically structured sensor based on carbon-nanocoils

Multi-function sensors are important in smart devices and integratable systems. However, achieving both high sensing performance and decoupling between signals with a simple device structure and circuit layout remains a great challenge. Herein, we developed an asymmetric “soft-hard” structured device composing of an elastic porous carbon-nanocoil (CNC)/polydimethylsiloxane (PDMS) pressure-sensitive layer and a relatively hard nonporous CNC/PDMS temperature-sensitive layer. The CNCs showed entanglement with one another and strong interaction with the PDMS matrix, and thus the thermal expansion of polymer induced considerable change of contact points and displacement of CNCs. This, along with the tunneling resistance effect, resulted in an ultra-high temperature sensitivity of 3045.95 % °C−1 and a high resolution of 0.05 °C. Meanwhile, the porous CNC/PDMS layer delivered a high capacitive pressure-sensing performance with a low detection limit of 1.5 Pa. Importantly, the layered soft-hard device structure with a shared-electrode layout enabled precise decoupling of temperature and pressure. Our sensor was further demonstrated in object sensing and picking tests, and successfully employed as a false-touch switch, showing its great potential in smart sensing and safety guarding systems.

Active Layer Thickness-Dependent Reliability of Solution-Processed Indium-Gallium-Zinc Oxide Thin-Film Transistors Under Bias Stress

Amorphous indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs) have been widely investigated because of their high carrier mobility and excellent uniformity. The IGZO TFTs’ device performances have significantly advanced, and commercial products based on IGZO TFTs have been released on the display market. On the other hand, solution-processed IGZO TFTs have also been researched to reduce fabrication costs [1]. However, the electrical properties and reliability of solution-processed IGZO TFTs should be improved for display applications compared to vacuum-processed IGZO TFTs. Because the IGZO layer is deposited using different processes, the improvement method of device performance should be investigated considering the solution process characteristics compared to the vacuum process.The thickness control method is one of the different points between the solution and vacuum process. In the vacuum process, the deposition time can control the layer thickness. However, the thickness of the solution-processed IGZO layer can be controlled by the layer stacking or the molarity of the precursor solution. Then, the thin film properties of the solution-processed IGZO layer can be varied depending on thickness. Therefore, the effect of thickness on the IGZO thin film properties should be considered when investigating the device performances of solution-processed IGZO TFTs with different active layer thicknesses.In this study, we investigated the reliability of solution-processed IGZO TFTs under bias stress as active layer thickness varied. Solution-processed IGZO TFTs were fabricated on a heavily doped p-type silicon wafer and thermally grown silicon dioxide using the gate electrode and gate insulator, respectively. The IGZO layer was deposited via a spin coating process using the precursor solution, which was prepared by dissolving indium acetate, gallium nitrate, and zinc acetate into 2-methoxyethanol. After annealing and patterning the IGZO layer, aluminum source and drain electrodes were deposited using thermal evaporation. We controlled the thickness of the solution-processed IGZO layer by controlling the molarity of the precursor solution and fabricated IGZO TFTs with active layer thicknesses of 15 and 80 nm.Solution-processed IGZO TFTs with a thick active layer (Device A) exhibited a negatively shifted threshold voltage and low field-effect mobility compared to devices with a thin active layer (Device B). Moreover, Device A was more significantly influenced by the constant bias stress than Device B. The threshold voltage shift (ΔV th) of Device A was 29.6 V, and that of Device B was 19.8 V, as shown in Figure 1. In other words, the reliability of solution-processed IGZO TFTs was degraded as the active layer thickness increased. The results of electrical properties and reliability of solution-processed IGZO TFTs with different active layer thicknesses were closely related to the defect state level of the IGZO layer. We analyzed the density-of-states (DOS) of solution-processed IGZO TFTs with different active layer thicknesses using the field-effect method [2]. Devices A and B exhibited DOS levels of 1.8×1017 and 9.8×1015 cm-3eV-1, respectively. In other words, the defect states increased as the thickness of solution-processed IGZO TFTs increased. The DOS variations depending on the IGZO layer thickness were attributed to the pin holes or disorder formed during the IGZO layer deposition process. Consequently, we concluded that the thin-film properties, including the DOS level, should be carefully controlled when controlling the active layer thickness to obtain high-performance solution-processed IGZO TFTs. Figure 1

Electromagnetic Coils for a 3000 Psi Hydraulic MEMS Valve Assembly

Electromagnetic coils serve many roles in MEMS technologies such as actuators, microfluidics, sensors, energy harvesting, wireless communication, inductive heating, and biomedical applications. Coils can be made using traditional semiconductor manufacturing techniques requiring near UV lithography to define photoresist molds, electroforming metal into the molds, chemical mechanical planarization, assembly, and packaging. Non-traditional techniques such as LIGA using x-rays and soft LIGA using near UV exposures can create higher aspect ratio structures therefor maximizing coil performance and minimizing coil size.Our work explores micro-fabrication techniques using soft LIGA lithography to create single sided and double-sided copper electroformed MEMS coils. The target coil feature sizes are 100+ micron in thickness of copper, 50 micron feature size, 50 micron gaps, and millimeters in total form factor. The microfabrication process including lithography, copper electrodeposition, and through wafer vias will be discussed along with lessons learned to meet the design criteria. Our goal is the demonstration of a single sided coil and double-sided coil device that could be assembled and arrayed across a 6 inch silicon wafer microfabrication process to create a hydraulic valve assembly. This would enable a digital flow control high-pressure hydraulic valve system capable of reaching 3000 psi. Ultimately this goal minimizes size and weight while increasing efficiency and maximizing power. The figure below depicts a cross sectional view of a single sided coil design assembled with a device layer having a through-wafer etch flow path.Figure 1: Cross sectional view showing a single hydraulic MEMs valve assembly. A single sided MEMs coil on top, a suspended spring able to open and close the valve, and a thru-wafer fluid flow path. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525. Figure 1

(Invited) Porous Semiconducting Nanotube Interfaces for Device Applications

Non-lithographic routes to creating curved, non-planar nanostructures and associated interfaces are appealing from both fundamental scientific and applied technological perspectives. For some time, we have been interested in the creation of hollow Si nanotubes with sensitive control of inner tube diameter, wall thickness, and tube length using the sacrificial etching of zinc oxide (ZnO) from Si-coated ZnO nanowires (NWs). With suitable nanotube wall thinness (< 10 nm), porosity in the sidewall morphology is retained as well (pSiNTs). Such structures have been exploited for selected applications relevant to drug delivery1, lithium storage/recycling,2 and optoelectronics/solar cells.3 For the latter category, charge carrier energetics also require careful control of the interfacial composition of the surrounding layers as well as their structure. This is especially true for semiconductors known as metal halide perovskites, where power conversion efficiencies (PCEs) for solar cells above 30%4 and external quantum efficiencies (EQEs) for LEDs above 10% have been reported recently.5 In this work we demonstrate proof-of-concept for nanotube geometries of such devices produced non-lithographically by creating porous nanotubes of either CeO2 or NiO following the sacrificial templating process outlined above, followed by formation of selected perovskites (MAPbI3 or MAPbBr3) within their hollow interior. Structural characterization and evaluation of their respective performance as a PV cell (MAPbI3/CeO2) or LED (MAPbBr3/NiO) is described, along with possible refinements and/or opportunities for the future.As an n-type semiconductor, the thermal stability and transparency of cerium oxide makes it an excellent candidate as an electron transport layer (ETL), and in planar perovskite solar cells it has been shown to offer protection of perovskites to UV light, heat, and moisture degradation. Cerium oxide was deposited onto the ZnO nanowires (100 nm diameter) by a spin coating process using a dilute solution of Ce3+, followed by OH- addition, ample rinsing to remove excess precursors, thereby forming cerium hydroxide on the surface of the ZnO NW (1 cycle). This process can be repeated amply until the desired wall thickness is obtained. To obtain CeO2, it is necessary to anneal the cerium hydroxide at 500°C in air. CeO2 NTs are subsequently formed by etching away the ZnO core with 1% HCl.Sidewall porosity facilitates formation of a desired metal halide perovskite (such as MAPbI3) by infiltration of a precursor solution, spin coating to remove excess, and thermal annealing at 500oC. Such MAPbI3/CeO2 NT structures have been thoroughly characterized by a combination of SEM, TEM, XRD, XPS, Raman, and PL spectroscopy. We use an inverted p-i-n configuration for an initial photovoltaic cell evaluation; specifically, a non-optimized device architecture of FTO-CuO-MAPbI3/CeO2 NTs-C60-Ag produces a Voc 0.81 ± 0.04 V and a PCE % 11.32 ± 1.35.From the complementary perspective of a hole transport layer for perovskite devices, one appealing candidate is nickel oxide (NiO) in nanotube form: it has high carrier mobility, good stability and processability; prior successful use in planar devices with suitable band level energetics has been demonstrated; and its use avoids the hygroscopic and acidic substrate-degrading nature of organic counterparts such as PEDOT:PSS. Similar to the CeO2 system, formation of NiO NTs is achieved by controlled exposure of preformed ZnO NW arrays to dilute aqueous solutions of a suitable metal salt (in this case nickel chloride) which is then followed by base exposure, wash steps, and a thermal anneal (at 500°C) to form a Ni(OH)2 shell. Etching in 1% HCl then occurs (to remove the ZnO), followed by another 500oC anneal, thereby creating the desired NiO NT. Nanotube wall thickness is controlled by duration of Ni precursor solution exposure. These pNiO NTs have been characterized by a combination of SEM, TEM, XRD, and XPS. Infiltration of these NTs to suitable perovskite precursors, followed by wash steps and a thermal anneal yields nanoscale MAPbBr3 formed within porous NiO nanotubes. Utilizing a device configuration of FTO/TiO2/MAPbBr3-pNiOx NTs/Spiro-OMeTAD/Ag, measurement of the electroluminescence (EL) properties of MAPbBr3 in these porous NiO nanotubes reveal a current efficiency (CE) of 5.99 Cd/A and external quantum efficiency (EQE) of 3.9%.Refinement of each type of structure, including interfacial chemical modification to reduce defects at these curved surfaces, is underway. REFERENCES T. Le, R. Gonzalez-Rodriguez, and J.L.Coffer, Pharmaceutics, 2019, 11, 571.T. Tesfaye, R. Gonzalez-Rodriguez, J.L. Coffer, T. Djenizian, ACS Appl. Mater. Interfaces, 2015, 7, 20495-20498.R. Gonzalez-Rodriguez, N. Arad-Vosk, A. Sa'ar, J.L. Coffer, J. Phys. Chem. C , 2018, 122, 20040-20045.Mariotti, E. Köhnen, F. Scheler, K.Sveinbjörnsson, L. Zimmermann, et al. Science, 2023, 381,63-69.Y. Liu, J. Cui, K. Du, et al. Nat. Photonics, 2019,13, 760–764. Figure 1

Ultrathin Gallium Oxide As a Gate Dielectric and Passivation Layer for Two-Dimensional Devices with Conductive Filament Contacts

Two-dimensional (2D) transition metal dichalcogenides (TMDs) are generally regarded as the channel material for post-silicon nanoelectronics owing to their distinctive crystal structure consisting of atomically thin dangling-bond-free layers, tunable bandgap and high carrier mobility. However, 2D devices based on TMDs typically suffer from performance degradation due to unwanted atmospheric reactions or adsorbates and require surface passivation to ensure that device performance is maintained. Recently, ultrathin metal oxides obtained through liquid metal printing or squeezing technique have emerged as a new class of 2D material with nanometer-scale thickness and large-area uniformity. Among them, ultrathin amorphous gallium oxide (GaOX) has garnered significant attention for its ease of fabrication owing to the low melting point of gallium (29.76 °C), large bandgap, and unique insulating and passivating properties. The ultrathin GaOX has been utilized for large-area passivation of 2D materials and as a dielectric for wide bandgap semiconductor devices. However, the integration of the ultrathin GaOX with 2D devices based on TMDs has rarely been investigated. In this study, we fabricated 2D devices based on multilayer n-type tungsten disulfide (WS2), wholly enveloped by the ultrathin GaOX. The ultrathin GaOX served as a dielectric passivation layer in the gate and channel region, whereas conductive filaments (CFs) were created in the ultrathin GaOX in the contact region through electroforming to form electrical contacts to the passivated WS2.The WS2 multilayers for the channel were mechanically exfoliated from its bulk crystal and were aligned to and dry-transferred onto pre-patterned Ti/Pt bottom electrodes on Si/SiO2 substrates. Liquid gallium droplets were placed on prepared polydimethylsiloxane (PDMS)/polypropylene carbonate (PPC) films and were firmly compressed using a PDMS film supported on a glass slide to produce ultrathin GaOX monolayers. The fabricated ultrathin GaOX monolayers were dry-transferred onto the prepared WS2 channels by utilizing the PPC film as a sacrificial layer. The ultrathin GaOX monolayers were slowly lowered to fully contact the prepared substrates, after which the substrates were heated to 90 °C to soften and release the PPC films from the PDMS films. The PPC films held down the ultrathin GaOX monolayers on the substrates during the detachment of the PDMS films and were removed later by immersion in acetone. This process was repeated twice to form the ultrathin GaOX bilayers on the WS2 channels. Ti/Au drain and source top electrodes were formed above the Ti/Pt bottom electrodes before Ni/Au top-gate electrodes were formed to finalize the WS2/GaOX field-effect transistors (FETs). CF contacts to the drain and source region of the passivated WS2 channels were created via electroforming, where positive and negative bias voltages were applied to the top electrodes with the corresponding bottom electrodes grounded.The ultrathin GaOX monolayer (~4.7 nm) and bilayer (~10.1 nm) fabricated in this work were determined to be highly uniform with root-mean-square roughness of 0.45–0.57 nm using atomic force microscopy. The ultrathin GaOX bilayer was evaluated via X-ray photoelectron spectroscopy to have an oxygen-deficient chemical composition with a sub-stoichiometric Ga:O ratio of 42:58 (Ga2O2.8). From the capacitance–voltage and current–voltage analyses of Pt/GaOX/graphene metal–insulator–metal devices, dielectric constant of 3.1 and dielectric breakdown voltage of +8 V were extracted for the ultrathin GaOX bilayer, respectively. The electroforming process of the ultrathin GaOX bilayer in the contact region of the WS2/GaOX FETs was irreversible, only showing decrease in the resistance during consecutive sweeps regardless of the polarity of the applied bias voltages. After the CF formation in ultrathin GaOX bilayers in the contact region, the electrical properties of WS2/GaOX FETs were investigated. The devices exhibited excellent top-gated performance with low subthreshold swing of 68.0–84.6 mV/dec and minimal hysteresis of 0.10–0.12 V. Furthermore, the CF contacts and the devices exhibited great electrical stability even after 50 days. Also, dual-gate logic operations of AND gate and OR gate were demonstrated using both the top and back gates of the WS2/GaOX FETs. This study demonstrates the implementation of the ultrathin GaOX as a gate dielectric, a passivation layer, and a CF contact layer in a single 2D device structure. The WS2/GaOX FETs exhibited outstanding electrical characteristics and stability, indicating the successful implementation and the versatility of the ultrathin GaOX. These results indicate the potential of the ultrathin GaOX as a key component in future 2D electronics.

A Simple in-situ Voltage Characterization Technique and Coating Methods for Developing Polymer Electrolyte Membrane Water Electrolysis Porous Transport Layer and Bipolar Plates

As climate change progresses, decarbonization becomes imperative, and hydrogen is gaining attention as a clean energy source alongside carbon [1]. Particularly, hydrogen obtained through electrolysis has the advantage of being carbon-free throughout the production process, known as green hydrogen. Currently, electrolysis is primarily conducted through alkaline and polymer electrolyte membrane methods. Polymer electrolyte membrane devices, operating effectively even at high pressures, offer advantages over alkaline electrolysis in efficiency and hydrogen production. Thus, polymer electrolyte membrane devices are essential for entering carbon neutrality [2]. However, the high voltage (~2V) and acidic operating environment in the operating condition causes component corrosion, forcing their uses of high price materials. The porous transport layer and bipolar plates of polymer electrolyte membrane devices utilize platinum-coated titanium [3]. Therefore, accurately measuring the voltage profile inside the device and replacing precious metal coated titanium can reduce device costs and offer commercial advantages. Although considerable research is ongoing, most studies require complex electrolyte solutions and custom membrane electrode assembly fabrication techniques.This study proposes a simple technique using commercial products to evaluate internal voltage profile in polymer electrolyte membrane devices and introduces materials that can replace titanium. Membrane Electrode Assembly from HIAT and Porous Transport Layer from Mott is utilized, and similar to Z. Kang et al. [4], voltages of the PTL, Catalyst Layer (CL), and Bipolar Plate (BP) relative to the cathode were measured. 0.001x0.005 mm² gold wire (California fine wire Co.) is used to measure voltage during the voltage. In some studies, voltage profiles of PEMWE stack were measured by applying voltage to the MEA instead of the bipolar plate [5]. In this study, voltage profiles inside of the cell and stack was measured. By simply placing a gold wire between the component, the voltage profile during device operation was observed. The measurements revealed a voltage small drop within the proton exchange membrane.On the other hand, the Ta-based stainless steel confirms the potential utilization of stainless steel coated materials as an alternative to titanium-based ones. According to Becker et al. [6], the voltage of the cathode during operation is approximately 0VvsRHE or less, and the bipolar plate's condition is electrochemically stable compared to the anode. Thus, a single-layer coating of PEALD TiN on stainless steel has been proposed for the cathode. On the contrary, the environment at the anode was harsher compared to the cathode, with a higher susceptibility to corrosion due to the application of high voltages (~2V). Therefore, a Ta based coating has been proposed for the anode. When conducting PEMWE experiments using Ta-coated stainless steel (SUS), it exhibited performance comparable to using Ti-based bipolar plates in both cell and stack performance. Moreover, in long-term performance, Ta-coated SUS demonstrated superior performance. Furthermore, coating Ta onto SUS PTL used in AEMWE confirmed the feasibility of replacing Ti-based PTL.References.[1] Y. Leng, P. Ming, D. Yang, C. Zhang, Stainless steel bipolar plates for proton exchange membrane fuel cells: Materials, flow channel design and forming processes, J. Power Sources. 451 (2020) 227783. https://doi.org/10.1016/j.jpowsour.2020.227783.[2] S.Y. Kang, J.E. Park, G.Y. Jang, C. Choi, Y.H. Cho, Y.E. Sung, Directly Coated Iridium Nickel Oxide on Porous-Transport Layer as Anode for High-Performance Proton-Exchange Membrane Water Electrolyzers, Adv. Mater. Interfaces. 10 (2023). https://doi.org/10.1002/admi.202202406.[3] H. Becker, E.J.F. Dickinson, X. Lu, U. Bexell, S. Proch, C. Moffatt, M. Stenström, G. Smith, G. Hinds, Assessing potential profiles in water electrolysers to minimise titanium use, Energy Environ. Sci. 15 (2022) 2508–2518. https://doi.org/10.1039/d2ee00876a.[4] Z. Kang, S.M. Alia, M. Carmo, G. Bender, In-situ and in-operando analysis of voltage losses using sense wires for proton exchange membrane water electrolyzers, J. Power Sources. 481 (2021) 229012. https://doi.org/10.1016/j.jpowsour.2020.229012.[5] A.J. McLeod, L. V. Bühre, B. Bensmann, O.E. Herrera, W. Mérida, Anode and cathode overpotentials under accelerated stress testing of a PEM electrolysis cell, J. Power Sources. 589 (2024). https://doi.org/10.1016/j.jpowsour.2023.233750.[6] H. Becker, E.J.F. Dickinson, X. Lu, U. Bexell, S. Proch, C. Moffatt, M. Stenström, G. Smith, G. Hinds, Assessing potential profiles in water electrolysers to minimise titanium use, Energy Environ. Sci. 15 (2022) 2508–2518. https://doi.org/10.1039/d2ee00876a.

Integration of a-InWZnO Thin Film Transistor with Copper Conductive Bridge Random Access Memory for Low Power Consumption Displays

In the era of big data and AI, the demand for information transmission has soared, leading to a surge in portable and wearable devices while traditional signage is gradually giving way to display devices. While these display devices offer rapid information transmission, they also pose energy consumption challenges. To address this, the Memory-in-Pixel (MIP) circuit concept is introduced to reduce display power consumption. However, traditional MIP circuits using static random-access memory (SRAM) components require a minimum of 6 Thin Film Transistors (TFT) devices for memory functions [1]. This complexity in device count complicates the manufacturing process of display circuits and limits display resolution due to the large circuit area they occupy.Conductive Bridge Random Access Memory (CBRAM) has emerged as a notable non-volatile memory due to its simple Metal-Insulator-Metal (MIM) structure, low power consumption, ease of fabrication, and compatibility with other processes [2]. Meanwhile, thin film transistors (TFTs) are widely employed as driving and switching devices in display circuits. Among these, Transparent Amorphous Metal Oxide Semiconductor (TAOS) TFTs stand out as highly promising for the next generation, offering advantages such as a high energy gap in channel materials, visibility to visible light, simplified large-area manufacturing, and superior carrier mobility.Notably, in addition to their efficacy as channel materials for TFTs, TAOS materials exhibit exceptional performance as a switching layer for CBRAM [3]. This led us to integrate a CBRAM with a TFT, forming a 1T1R structure capable of both memory storage and driving functionalities. For the active layers of this 1T1R device, we utilized the emerging TAOS material amorphous indium tungsten zinc oxide (InWZnO, IWZO) as the switching and channel layer.To enhance CBRAM performance, we introduced an ultrathin TiO2 dielectric into the switching layer. Furthermore, we explored the impact of the thickness of the IWZO switching layer on CBRAM characteristics. Regarding TFT components, we fine-tuned the sputtering conditions of the IWZO layer to optimize electrical characteristics and driving capabilities. Ultimately, the CBRAM and TFT devices exhibiting the best performance were integrated into the 1T1R structure.Based on experimental results, we significantly improved the DC endurance cycles of our CBRAM with the TiO2 insertion layer while reducing operating voltage and limiting current. This optimized CBRAM and TFT combination resulted in low operating power consumption (~20 μW) and holds promise for low-power MIP display circuits. Reference: [1] S. H. Lee, B. C. Yu, H. J. Chung, and S. W. Lee, “Memory-in-pixel circuit for low-power liquid crystal displays comprising oxide thin-filmtransistors,” IEEE Electron Device Lett., vol. 11 (11), pp. 1551–1554, 2017.[2] K. J. Gan, P. T. Liu, D. B. Ruan, Y. C. Chiu, Simon M. Sze, “Annealing effects on resistive switching of IGZO-based CBRAM devices,” Vacuum, vol. 180, 109630, 2020.[3] C. C. Hsu, P. T. Liu, K. J. Gan, D. B. Ruan, Simon M. Sze, “Investigation of deposition technique and thickness effect of HfO2 film in bilayer InWZnO-based conductive bridge random access memory”, Vacuum, vol. 201, 111123, 2022.

(Invited) Study on Rram Properties Using Resistive Switching Layer with ZnO Nanostructure

Zinc oxide (ZnO) is an amorphous oxide semiconductor (AOS) material valued for its high carrier mobility, transparency to visible light, and low-temperature manufacturing process compared to silicon-based semiconductors. These desired features make ZnO-based AOSs widely popular as the channel layer in TFTs and as key dielectric layers in electronic devices like light sensors, gas detectors, resistive random-access memory (RRAM), and more. Among them, Conductive Bridge Random Access Memory (CBRAM) with a dielectric switching layer sandwiched between the electrochemically active metal (Ag, Cu) top electrode and the inert bottom electrode, is of a class of RRAM that offers low-voltage operation, high-density storage device, non-volatile, and compatibility with standard CMOS processes [1]. The CBRAM operates based on the principle of conductive filament formation and rupture. During operation, conductive filaments will be formed in switching layer by connecting metal ions which diffuse from the electrode after applying a positive bias. The device will switch to a low resistance state (LRS) after the conductive filaments were formed. After this, applying a negative bias will break the conductive filaments and switch the device back to a high resistance state (HRS). The HRS and LRS are the 0 or1 state of the memory operation. Studies and works have shown that controlling the distribution and diffusion of electrode metal ions in the switching layer is challenging because the conductive filaments formed can vary significantly in strength, ranging from robust to fragile [2]. This leads to instability in the operation of memory devices and encountering difficulties in the integration with TFT pixel array for memory-in-pixel (MiP) power-saving displays [3] or CMOS-integrated compute-in-memory applications [4].In this work, we proposed a novel CBRAM device featuring ZnO nanostructures as the resistive switching layer. The combination of a sputter-deposited seed layer with the water bath method enables the production of high-quality ZnO nanostructures at temperatures below 90°C. These nanostructures play a crucial role in constraining metal ion diffusion and filament formation, leading to the formation of uniform conductive filaments. This improvement significantly enhances the operational stability of the CBRAM device. The experimental results have demonstrated superior memory characteristics with a highly uniform distribution achieved successfully in the ZnO nanostructure-embedded CBRAM, compared to its counterpart lacking ZnO nanostructures. Furthermore, post-treatments are implemented in this study to further promote electrical performance of the nanostructure-embedded CBRAM, like operation voltage, memory window, retention, and endurance. Reference: [1] C. Gopalan, Y. Ma, T. Gallo, J. Wang, E. Runnion, J. Saenz, F. Koushan, P. Blanchard, S. Hollmer, “Demonstration of Conductive Bridging Random Access Memory (CBRAM) in logic CMOS process”, Solid-State Electronics, vol. 58 (1), p. 54-61, 2011.[2] C. C. Hsu, P. T. Liu, K. J. Gan, D. B. Ruan, Simon M. Sze, “Investigation of deposition technique and thickness effect of HfO2 film in bilayer InWZnO-based conductive bridge random access memory”, Vacuum, vol. 201, 111123, 2022.[3] S. H. Lee, B. C. Yu, H. J. Chung, and S. W. Lee, “Memory-in-pixel circuit for low-power liquid crystal displays comprising oxide thin-filmtransistors,” IEEE Electron Device Lett., vol. 11 (11), pp. 1551–1554, 2017.[4] W. Wan, R. Kubendran, C. Schaefer, et al., “A compute-in-memory chip based on resistive random-access memory”, Nature, vol. 608, p. 504–512, 2022.

Effect of Local pH Change on Galvanostatic Deposition of n-Type Cu2o in Acidic Media: A Chronopotentiometry Study

N-type cuprous oxides (Cu2O) were electrodeposited on Fluorine-doped Tin Oxide (FTO) coated glass substrate in acidic media. We investigated the chrono-potentiometry behavior of the deposited Cu2O films across various current densities. Lower current densities exhibited stable potentials, while higher densities resulted in sharp spikes followed by stabilization. Notably, our study in an acidic medium did not manifest potential oscillations typically observed in alkaline systems. Remarkably, we observed negative potential spikes in the chronopotentiometry curve, particularly at higher current densities exceeding -0.2 mA cm-2, which remains a highlight of our findings. The potential spike indicates the likelihood of a second reaction, the formation of Cu. We argue that the formation of Cu originates from the reduction of Cu2O rather than bulk deposition, primarily due to the change in local pH near the working electrode during the Cu2O deposition process. Continuous stirring of the electrolyte aids in delaying the Cu2O to Cu conversion reaction (Cu2O corrosion), with further influence observed by altering the rotation speed during stirring. Unlike the well-explored galvanostatic deposition of Cu2O in basic media, the behavior of such deposition in acidic media remains largely unexplored. Our study provides insights into the formation of phase-pure n-type Cu2O and obviates the occurrence of the speculated second reaction, Cu2O corrosion. Phase-pure n-type Cu2O enables investigations into defect chemistry governing n-type behavior without metallic Cu complications. It serves as an electron transport layer in photo-conversion devices and allows for homojunction devices with p-type Cu2O. Figure 1