Integration of a-InWZnO Thin Film Transistor with Copper Conductive Bridge Random Access Memory for Low Power Consumption Displays

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In the era of big data and AI, the demand for information transmission has soared, leading to a surge in portable and wearable devices while traditional signage is gradually giving way to display devices. While these display devices offer rapid information transmission, they also pose energy consumption challenges. To address this, the Memory-in-Pixel (MIP) circuit concept is introduced to reduce display power consumption. However, traditional MIP circuits using static random-access memory (SRAM) components require a minimum of 6 Thin Film Transistors (TFT) devices for memory functions [1]. This complexity in device count complicates the manufacturing process of display circuits and limits display resolution due to the large circuit area they occupy.Conductive Bridge Random Access Memory (CBRAM) has emerged as a notable non-volatile memory due to its simple Metal-Insulator-Metal (MIM) structure, low power consumption, ease of fabrication, and compatibility with other processes [2]. Meanwhile, thin film transistors (TFTs) are widely employed as driving and switching devices in display circuits. Among these, Transparent Amorphous Metal Oxide Semiconductor (TAOS) TFTs stand out as highly promising for the next generation, offering advantages such as a high energy gap in channel materials, visibility to visible light, simplified large-area manufacturing, and superior carrier mobility.Notably, in addition to their efficacy as channel materials for TFTs, TAOS materials exhibit exceptional performance as a switching layer for CBRAM [3]. This led us to integrate a CBRAM with a TFT, forming a 1T1R structure capable of both memory storage and driving functionalities. For the active layers of this 1T1R device, we utilized the emerging TAOS material amorphous indium tungsten zinc oxide (InWZnO, IWZO) as the switching and channel layer.To enhance CBRAM performance, we introduced an ultrathin TiO2 dielectric into the switching layer. Furthermore, we explored the impact of the thickness of the IWZO switching layer on CBRAM characteristics. Regarding TFT components, we fine-tuned the sputtering conditions of the IWZO layer to optimize electrical characteristics and driving capabilities. Ultimately, the CBRAM and TFT devices exhibiting the best performance were integrated into the 1T1R structure.Based on experimental results, we significantly improved the DC endurance cycles of our CBRAM with the TiO2 insertion layer while reducing operating voltage and limiting current. This optimized CBRAM and TFT combination resulted in low operating power consumption (~20 μW) and holds promise for low-power MIP display circuits. Reference: [1] S. H. Lee, B. C. Yu, H. J. Chung, and S. W. Lee, “Memory-in-pixel circuit for low-power liquid crystal displays comprising oxide thin-filmtransistors,” IEEE Electron Device Lett., vol. 11 (11), pp. 1551–1554, 2017.[2] K. J. Gan, P. T. Liu, D. B. Ruan, Y. C. Chiu, Simon M. Sze, “Annealing effects on resistive switching of IGZO-based CBRAM devices,” Vacuum, vol. 180, 109630, 2020.[3] C. C. Hsu, P. T. Liu, K. J. Gan, D. B. Ruan, Simon M. Sze, “Investigation of deposition technique and thickness effect of HfO2 film in bilayer InWZnO-based conductive bridge random access memory”, Vacuum, vol. 201, 111123, 2022.