Laterally Diffused Metal Oxide Semiconductor Research Articles

Research on single event effects and hardening design of LDMOS transistors

In this paper, an N-type Lateral Diffused Metal Oxide Semiconductor (LDMOS) device was designed using a heavily doped P+ well and drain N-type buffer layer structure in the BCD process. The hardened mechanism of heavily doped P+ well and drain N-type buffer layer structures was simulated and analyzed using a TCAD device simulator. To verify the anti-SEE performance of the LDMOS, the irradiation test was conducted using Ta ion (LET = 79.2 MeV·cm−2 mg−1). The results show that increasing P+ well doping concentration and using buffer layer structure can increase the single event burnout (SEB) voltage of high-voltage LDMOS devices. SEB did not occur within the full operation voltage range.

Enhancement of Electrical Safe Operation Area of 60 V nLDMOS by Engineering of Reduced Surface Electrical Field in the Drift Region.

To enhance the electrical safe operation area (eSOA) of laterally diffused metal oxide semiconductor (LDMOS) transistors, a novel reduced surface electric field (Resurf) structure in the n-drift region is proposed, which was fabricated by ion implantation at the surface of the LDMOS drift region and by drift region dimension optimization. Technology computer-aided design (TCAD) simulations show that the optimal value of Resurf ion implantation dose 1 × 1012 cm-2 can reduce the surface electric field in the n-drift region effectively, thereby improving the ON-state breakdown voltage of the device (BVon). In addition, the extended n-drift region length of the Ld design also improves device BVon significantly, and is aimed at reducing the current density and the electric field, and eventually suppressing the n-drift region impact ionization. The results show that the novel 60 V nLDMOS has a competitive BVon performance of 106.9 V, which is about 20% higher than that of the conventional one. Meanwhile, the OFF-state breakdown voltage of the device (BVoff) of 88.4 V and the specific ON-resistance (RON,sp) of 129.7 mΩ⋅mm2 exhibit only a slight sacrifice.

Influence of Hot Carrier Degradation on the Characteristics of a High-Voltage SOI Transistor with a Large Drift Region

The results of studying the effect of hot carrier degradation on the electrical characteristics of high-power laterally diffused metal oxide semiconductor (LDMOS) transistors made according to the silicon-on-insulator (SOI) technology, with a long drift region with topological norms of 0.5 microns, are discussed. The analysis of the degradation of hot carriers in high electric fields is based on the experimental results and the additional use of an analytical model. The physical origin of this mechanism is related to the formation of traps at the Si/SiO2 interface. With the help of numerical analysis and experiments, the electrical character-istics of SOI nLDMOS transistors are considered in a wide range of control voltages in order to study their effect on the safe operation zone and reliability of the device under conditions of the degradation of hot carriers. The results of these studies allow us to conclude that a 20% expansion of the safe operation zone is possible.

Numerical Investigation of Transient Breakdown Voltage Enhancement in SOI LDMOS by Using a Step P-Type Doping Buried Layer

In this paper, the transient breakdown voltage (TrBV) of a silicon-on-insulator (SOI) laterally diffused metal-oxide-semiconductor (LDMOS) device was increased by introducing a step P-type doping buried layer (SPBL) below the buried oxide (BOX). Device simulation software MEDICI 0.13.2 was used to investigate the electrical characteristics of the new devices. When the device was turned off, the SPBL could enhance the reduced surface field (RESURF) effect and modulate the lateral electric field in the drift region to ensure that the surface electric field was evenly distributed, thus increasing the lateral breakdown voltage (BVlat). The enhancement of the RESURF effect while maintaining a high doping concentration in the drift region (Nd) in the SPBL SOI LDMOS resulted in a reduction in the substrate doping concentration (Psub) and an expansion of the substrate depletion layer. Therefore, the SPBL both improved the vertical breakdown voltage (BVver) and suppressed an increase in the specific on-resistance (Ron,sp). The results of simulations showed a 14.46% higher TrBV and a 46.25% lower Ron,sp for the SPBL SOI LDMOS compared to those of the SOI LDMOS. As the SPBL optimized the vertical electric field at the drain, the turn-off non-breakdown time (Tnonbv) of the SPBL SOI LDMOS was 65.64% longer than that of the SOI LDMOS. The SPBL SOI LDMOS also demonstrated that TrBV was 10% higher, Ron,sp was 37.74% lower, and Tnonbv was 10% longer than those of the double RESURF SOI LDMOS.

A Broadband Power Amplifier With Multifrequency Impedance Matching

This letter proposes a multifrequency impedance matching broadband power amplifier (PA) design, which is different from the traditional PA impedance value changes with the change in the operating frequency. This method selects the impedance value of the transistor device through the load–pulling system. Then, matching networks composed of a cascade of microstrip lines are used to match the device impedance to 50 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> . The matching networks are optimized to provide the desired impedance transfer characteristic at multiple frequencies. This design approach effectively reduces the amplifiers’ output impedance variation over the covered frequency range. The overall structure of the PA is simple, and the bandwidth is expanded while ensuring performance. Based on this method, a broadband PA was designed and fabricated using the self-developed laterally-diffused metal-oxide semiconductor (LDMOS) transistor of the Institute of Microelectronics of the Chinese Academy of Sciences. The measurement results show that the saturated output power of the designed PA in the range of 0.5–2.3 GHz is greater than 41 dBm. The drain efficiency is 43.62%–55.38%. When the average output power is 34.3 dBm, the adjacent channel leakage ratio (ACLR) is also better than −31.58 dBc.

Comprehensive study of the radiation effects on the LDMOS transistors

The reliability of power devices is attracting more and more attention, especially in the extreme radiation environment. The laterally diffused metal–oxide–semiconductor (LDMOS) has been widely used in high voltage integrated circuits. In this paper, the radiation effects of LDMOS transistors are extensively investigated through three-dimensional (3D) TCAD simulations, including Total-Ionizing Dose (TID), Single-Event Effect (SEE) and Transient Dose Rate Effect (TDRE). Firstly, the mechanism of TID effect on the LDMOS is revealed in consideration of temperature variations. Secondly, the single-event effect of the LDMOS is studied with different incident positions, linear energy transfer (LET) values, incident lengths, incident angles, bias conditions and temperatures. Besides, the combined effect of total-ionizing dose and single-event burnout is characterized. Finally, transient response of the LDMOS under transient γ radiation is also studied comprehensively. Therefore, it gives an insight into the physical mechanisms and response characteristics of complex radiation effects, which can provide guidance for radiation-hardened by design and application of the LDMOS devices.

A Novel Ga2O3 Superjunction LDMOS Using P-Type Diamond with Improved Performance

Gallium oxide (Ga2O3) has drawn remarkable attention for next generation power electronics applications. However, the development of Ga2O3 power devices is seriously restricted due to its inefficient p-type dopants and low thermal conductivity. In this article, a novel Ga2O3 superjunction (SJ) LDMOS (laterally-diffused metal-oxide semiconductor) device with introduction of a p-type diamond layer in the drift region is proposed and numerical investigated. The drift region of the proposed Ga2O3 device consists of n-type Ga2O3, Al2O3 and p-type diamond, which is not only increases the breakdown voltage (BV) and reduces the specific on-resistance (R on,sp), but also improves thermal performance of the device. The simulation results show that the BV and R on,sp of the proposed device are 23.22 mΩ·cm2 and 7000 V, which are improved by more than 82.3% and 133% compared with those the conventional gate-connected filed-plate Ga2O3 lDMOS with a R on,sp of 131.43 mΩ·cm2 and a BV of 3000 V, respectively. Moreover, the thermal performance of the proposed Ga2O3 SJ LDMOS is also improved dramatically, although the power density of the proposed device is about 5.7 times higher than that of the conventional device.

Novel Step Field Plate RF LDMOS Transistor for Improved BVDS-R on Tradeoff and RF Performance

In this article, a novel step field plate (SFP) laterally diffused metal–oxide–semiconductor (LDMOS) structure is proposed for improved breakdown voltage- ON resistance tradeoff and better RF performance. The proposed structure could be easily integrated into the CMOS process flow using four additional noncritical masks. The known materials like fully silicided polysilicon and silicon nitride (SiN) are used as FP and dielectric, respectively. The proposed design improves the device performance by uniformly distributing the electric field in the drift region. The higher drift doping for the same OFF-state breakdown voltage improves the ON resistance by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 2.5\times $ </tex-math></inline-formula> and ON-state breakdown voltage by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 2\times $ </tex-math></inline-formula> . Significant improvements in frequency behavior and flat power response are also observed. The device physics behind different observations are explained using detailed TCAD simulations.

A simulation-based evaluation of single-event burnout mechanisms and varied SEB hardening designs in power LDMOS transistors

In this paper, the Single-event burnout (SEB) triggering mechanism for laterally-diffused metal-oxide semiconductor (LDMOS) devices is numerically studied by using the 2D technology computer-aided design device simulator, simultaneously, three hardening designs are proposed for the first time. SEB triggering voltage (VSEB) are extracted and compared between the four structures when the heavy ion with a same linear energy transfer (LET) of 0.2pC/μm strikes the most sensitive point of the devices. The occurrence mechanism of SEB in LDMOS is mainly due to avalanche breakdown caused by high electric field, which further triggers the parasitic BJT and eventually forms regenerative feedback. By comparing the simulation results between conventional LDMOS and proposed hardened LDMOS designs, the VSEB are 197 V of conventional LDMOS, 306 V of NB LDMOS, 291 V of NP LDMOS and 394 V of NP-BP LDMOS, and their breakdown voltage(BV) are 650 V,606 V, 555 V and 553 V respectively. With different LET values, NB LDMOS and NP LDMOS also have better SEB performance than the conventional one.

The Root Cause Behind a Peculiar Dual-Mode ON-State Breakdown in High Voltage LDMOS

This work investigates the often-observed current discontinuity much before avalanche breakdown (dual-mode ON-state breakdown) in the output characteristics of a laterally diffused metal–oxide–semiconductor (LDMOS) device. The physical origin of the dual-mode ON-state breakdown, often reasoned to be due to parasitic n-p-n, is shown to be independent of parasitic n-p-n. A laterally diffused tunnel FET (LDTFET) with a drift region profile same as LDMOS was experimented to rule out the effect of parasitic n-p-n. LDTFET device, which intrinsically cannot have parasitic n-p-n, also shows similar output characteristics with dual-mode ON-state breakdown. This proved that the parasitic bipolar turn-on is not the root cause behind the observed behavior. On the contrary, it was found to be dependent on the onset of space charge modulation (SCM) in the drift region, resulting in localized high electric field and quasi-saturation effects at low drain voltages. The effect of mobility degradation due to the high electric field in the drift region post-SCM is also presented, emphasizing that the observed behavior results from the high field mobility degradation of majority charge carriers.

Study on 20 V LDMOS With Stepped-Gate-Oxide Structure for PMIC Applications: Design, Fabrication, and Characterization

In this brief, a 20 V laterally diffused metal-oxide-semiconductor (LDMOS) device with the concept of stepped-gate-oxide (SGO) was fabricated with standard 0.15 μm BCD technology. Compared with the conventional shallow-trench-isolation LDMOS (STI-LDMOS), the SGO structure features a straight conduction path on a silicon surface, based on our past development experience, and therefore, an ON-resistance reduction of about 20% can be obtained. This brief demonstrated the LDMOS from a power-switching perspective, considering both optimization design and characterization aspects. The optimum device was demonstrated with R <formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex>$_{ON,sp}$</tex> </formula> of 4.92 mΩ ·mm², breakdown voltage (BV) of 23.8 V, and device figure of merit (FOM) of 20 mΩ -nC. By combining with optimum power stage design, the buck converter efficiency showed 93.88% at low load condition and 93.98% at high load condition, achieving an outstanding dc-dc converting performance.

Design and implementation of an S-band transmitter for nanosatellites with new configuration

In this paper, the author presents the design and implementation of an Sband transmitter for nanosatellites. By combining heterostructure field effect transistors (HFET) and laterally diffused metal–oxide–semiconductor (LDMOS) technology and using flexible structure and flexible control method, this research obtained 60 dB gain power when input is -14 dBm, output power is 46 dBm (more than 25 W) in 2,1 GHz -2,3 Ghz frequency; phase noise is -80 dBc/Hz at 100 KHz offset frequency. Unlike other traditional transmitters, this transmitter was designed with multi-stages which have multi-peaks resonance to expand bandwidth to respond to the requirement of generation of the complex signal in wide band. Moreover, the phase locked loop (PLL) in frequency synthesizer makes the frequency conversion more flexible and output frequency more stable; thermal problem in module also was solved by using thermistor and operation mode. Measurement results prove that the design does not only satisfy the requirements of nanosatellites but also can be applied to other satellites together with their ground station because it has open configure with flexible structure and flexible control method.

A 15 V-Tolerant and Radiation-Hardened MOSFET Driver With Positive and Negative References

Radiation-hardened and high-voltage power circuits are key components in aerospace applications. However, when working at high voltages, the effects of the total ionizing dose (TID) and the single event limit the application of power driving circuits in a radiation environment. A 15 V-tolerant radiation-hardened MOSFET driver was designed. The circuit architecture, which is based on positive and negative references, can reduce the gate source voltage of the transistors to less than 5&#x00A0;V, allowing the selection of thin-gate oxide high-voltage transistors. On this basis, adopting enclosed layout transistor (ELT) N-channel metal oxide semiconductor (NMOS) transistors helps the driver to obtain a good resilience to TID hardness. Additionally, this work optimized the layout of high-voltage N-type laterally diffused metal oxide semiconductor (LDMOS) transistors in the driver to effectively improve the single-event burnout (SEB) threshold. Three chips with different N-type drift region lengths were designed and fabricated in a 0.35&#x00A0;<inline-formula><tex-math notation="LaTeX">$\mu m$</tex-math></inline-formula> BCD process. The test results showed that the TID hardening capability of these chips with ZENER references and ELT NMOS transistors all exceeded 100 krad (Si). In addition, this driver was tested under heavy ion irradiation with linear energy transfer (LET) exceeding 75 MeV&#x00B7;<inline-formula><tex-math notation="LaTeX">$\dot\mathrm{{c}}{\mathrm{{m}}^{2}}\mathrm{{/mg}}$</tex-math></inline-formula>. The results show that this driver with a 6.6&#x00A0;<inline-formula><tex-math notation="LaTeX">$\mu m$</tex-math></inline-formula> drift region length had no single event latchup (SEL), single event gate rupture (SEGR), or single event burnout (SEB) sensitivity.

LDMOS Drift Region With Field Oxides: Figure-of-Merit Derivation and Verification

We analytically and numerically investigate the performance of Laterally-Diffused Metal-Oxide-Semiconductor (LDMOS) transistors with Semi-circular Field OXide (S-FOX) focusing on mid-voltage (30 V – 100 V) power applications. We derive an analytical relation between breakdown voltage and on-resistance to realize the ideal behavior of the drift region for an LDMOS with S-FOX. Then, we find the optimized drift doping concentration minimizing the on-resistance at a given breakdown voltage. We introduce a new figure-of-merit for the drift region of a lateral device with S-FOX. We finally verify our ideal analytical findings with numerical results modeled and simulated in a commercial Technology Computer-Aided Design (TCAD).

A novel SOI-LDMOS with field plate auxiliary doping layer that has improved breakdown voltage

Field plate (FP) is a widely used electric field optimization technique in lateral power devices. However, we found that the electric field distribution optimized by FP still has poor uniformity due to the excessive induced charges at the end of FP. To solve the problem, a novel silicon on insulator based lateral double diffused metal oxide semiconductor (SOI-LDMOS) with a field plate auxiliary doping layer (FPADL) is proposed. Our investigation proved that the FPADL introduces an additional part of space charge and partially balances the excessive induced charges at the end of FP. As a result, the FPADL introduces an additional electric field peak and improves the electric field distribution. Thereby, the SOI-LDMOS with FPADL has improved breakdown voltage (BV). The effect of FPADL is verified experimentally. In our experiment, the FPADL is realized by modifying the mask of buffer layer to avoid increasing the process cost. The measurement results showed that, comparing with the conventional SOI-LDMOS with FP, the proposed SOI-LDMOS with FPADL improved the BV by 9.52% with the on-resistance and the process cost maintained. Therefore, the proposed SOI-LDMOS with FPADL is a promising device.

Process and performance optimization of Triple‐RESURF LDMOS with Trenched‐Gate

In this article, we investigate by TCAD simulation, the combination triple reduced surface field (triple-RESURF) and trenched-gate to design an n-type laterally diffused metal-oxide-semiconductor (LDMOS) transistor with high performance. While similar structures reported in the literature, on the one hand, use either the triple-RESURF or trenched-gate at once, on the other hand, those features require at least one additional mask each. We have been able to achieve both features in one transistor with only eight masks at the front-end of line (FEOL), and one less annealing. Therefore, our proposition will be cheaper and provide better performance. The structure is obtained by re-organizing the process steps, re-using other existing masks, and exploiting positive and negative photoresist photolithography. The resulting specific on-state resistance (RON,SP) is 94 mΩmm2, and the breakdown voltage (BV) is 71 V. But, most importantly a high transconductance (gm) at high gate voltages, with acceptable off-state leakage current (Ioff), which translates into better RF performance overall than what is reported in the literature. The maximum oscillation frequency (fMAX) and cut-off frequency (fT) could reach up to 76 and 43 GHz, respectively. Our device targets fully integrated IoT ASICs that require power amplifiers.

Accurate Modeling Methodology of Laterally Diffused Metal-Oxide Semiconductor Leakage Current for Electro-Static Discharge Protection Circuit Design.

A modeling method using juncap2 physical compact model with SRH (Shockley-Read-Hall), TAT (Trap-Assisted-Tunneling), BBT (Band-to-Band Tunneling) effects is presented for the leakage current in a laterally diffused metal-oxide semiconductor (LDMOS). The juncap2 model is successfully combined with BSIM4 model and it is validated with measurement data. The model accurately predicts the leakage current characteristics for the entire bias region and temperature.

A Medium Power, Self-Sustaining, and Configurable RF Pulse Generation Circuit Using a Nonlinear Transmission Line and Power Amplifier in Open and Closed-Loop Configurations

Nonlinear transmission lines (NLTLs) are a class of pulse forming networks (PFNs) for modulation of pulsed power to generate radio frequency (RF) signals. Primarily, NLTL designs assume a two-port configuration, which requires ones-to-tens of nanosecond input pulse rise time for each modulated pulse out. In this article, a closed-loop or single-port pulser that yields continuous pulses based on prior pulse stimulation is presented. The pulser is comprised of an NLTL, a power amplifier (PA), and a solid-state HV pulse generator. The capability advantage of the closedloop system is its stability and center frequency tunability. Pragmatically, the solid-state-based design of this system enhances its probability of fielded use due to volume and mass savings compared to the prior art. The validity of the proposed design is empirically shown by a 16-section NLTL coupled with a solid-state laterally diffused metal-oxide-semiconductor (LDMOS)-based PA and a custom HV pulse generator. The closed-loop configuration constructed from these components demonstrated a peak power of 2.1 kW into 50 Ω at 90 MHz. This is the first report of a solid-state switch-based closed-loop NLTL configuration capable of producing a continuous pulse stream. Furthermore, we propose a dual-diode-based NLTL design, which can operate and output at higher center frequencies compared to its single-diode counterpart.

2.6-GHz Integrated LDMOS Doherty Power Amplifier for 5G Basestation Applications

This letter presents a compact output combining network for a packaged integrated asymmetric Doherty power amplifier (DPA) by taking advantage of device drain source capacitance, Cds and package parasitic components. A new method is introduced to/of/for absorbing part of the peaking amplifier's C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> ds</sub> into the impedance transformer, thus extending the C- L- C-based “ C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> ds</sub> -absorption” technique to two-way asymmetric DPAs. Based on the proposed combining network, a two-stage laterally-diffused metal-oxide semiconductor (LDMOS) integrated asymmetric DPA was designed and fabricated at 2.6 GHz. The fabricated RF integrated circuit (RFIC) is mounted in a quad flat no-lead (QFN) package. Under a single-tone continuous-wave (CW) signal at 2.6 GHz, the DPA achieves a peak power of 46 dBm, a linear gain of 31.7 dB, and a 48% power-added efficiency (PAE) at 8-dB output power back-off (OBO). The DPA also demonstrates good linearizability by meeting the 5G spectrum mask and achieving a digital predistortion (DPD) corrected adjacent channel power ratio (ACPR) better than -51.5 dBc for 160-MHz long-term evolution (LTE).

Deep neural network-based approach for breakdown voltage and specific on-resistance prediction of SOI LDMOS with field plate

Breakdown voltage (BV) and specific on-resistance (R on,sp), are critical indicators to measure the quality of the power device. To improve the device performance, field plate technology has been developed by modifying the electric field distribution. However, the current technology computer-aided design (TCAD) simulation cannot predict the effect of field plate on BV and R on,sp simultaneously, and the operation process is complicated. This paper proposes a deep neural network (DNN)-based model instead of TCAD to predict the effect of field plates on BV and R on,sp of silicon on insulator lateral double diffused metal oxide semiconductor. The experimental results show that, compared with TCAD simulation, the average deviation for BV and R on,sp is 5.06% and 2.55%, respectively. Also, the time for BV prediction is accelerated significantly up by 1.23 × 105. Our DNN model provides a potential direction to predict device performance with higher efficiency.