Lateral PNP Research Articles

Investigation of Neutron Displacement Effects in Bipolar Amplifiers With Lateral and Substrate p-n-p Input Transistors

Neutron displacement effects in LM158L and LM158V bipolar amplifiers with lateral p-n-p (LPNP) and substrate p-n-p (SPNP) input transistors, respectively, were investigated based on neutron irradiation experiments and TCAD simulation. Experimental results suggest that the type of input transistor of the amplifier has great impact on the neutron displacement degradation. The input bias current and input offset current of the amplifier with SPNP input transistor increase more than that with LPNP input transistor, and more severe degradation in SPNP than that in LPNP leads to the corresponding more severe degradation in the specific amplifier. TCAD simulations were performed to analyze the physical mechanism of neutron displacement effects in these two kinds of input transistors. For LPNP, the hole current is much closer to the surface of the silicon, however for SPNP, the hole current is much deeper into the bulk silicon, so the displacement traps in whole bulk all contribute to the total recombination. Therefore, the total recombination in SPNP is larger than that in LPNP, resulting in more severe degradation under neutron irradiation.

Exploration on Electrical Isolation Between High-Voltage SiC Thyristor and Small-Signal Devices for Smart Power Devices

The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Smart Discrete</i> concept which monolithically integrates a vertical high-voltage power device with low-voltage smart circuits has been widely adopted in silicon world for many years and may bring similar benefits to SiC world. For example, it is highly desirable to integrate a gate driver circuit onto a high-voltage SiC thyristor for ultra-fast turn-on. However, the electrical isolation between the vertical high-voltage power device and the low-voltage circuit elements remains a major technical challenge for silicon, and even more so for SiC due to the very limited processing options. In this article, we propose a combination of shallow junction isolation (JI) and partial dielectric isolation (DI) for high-voltage 4H-SiC smart thyristor, which is monolithically integrated with low-voltage nMESFET circuits. The characterization of fabricated devices and analysis of leakage currents across the isolation structure have been done to experimentally verify the feasibility of the isolation method. 8 V parasitic lateral NPNP thyristor between a 6.3 kV 4H-SiC thyristor and isolation moats, 175 V lateral PNP transistor between the passive resistor and isolation moats, and 10 V lateral reverse-biased p-n diode between nMESFET and isolation moats are experimentally demonstrated.

Novel dual-direction electrostatic discharge device with lateral PNP transistor

With the shrinking of semiconductor technology and the increasing of integrated circuits, electrostatic discharge (ESD) as a common natural phenomenon has become one of the main reasons for the failure and reliability reduction of electronic products in integrated circuits. A novel dual-direction ESD device (PNP_DDSCR) with embedded lateral PNP transistor is proposed for diminishing ESD damage. The response process and current transportation of PNP_DDSCR under different ESD stress modes are investigated. Comparative analyses between conventional DDSCR and PNP_DDSCR are executed by TCAD simulation. On the stage of device triggering, the embedded lateral PNP transistor inner DDSCR system provides triggering current for device. The injection efficiency of parasitic transistor in the DDSCR system is improved, and the positive feedback system is promoted. Thus, the holding voltage of PNP_DDSCR is higher than that of conventional DDSCR. At the same time, an extra triggering path introduced by embedded lateral PNP transistor of PNP_DDSCR makes the total triggering path of device shorten. Therefore, the transient overshoot voltage of PNP_DDSCR is lower than that of DDSCR. For thermal performance, most of the heat first accumulates near the lateral PNP transistor , and then the peak point of heat turns to main SCR path with the conduction of PNP_DDSCR. The heat accumulation in PNP_DDSCR is shared by the path of embedded lateral PNP transistor. As a result, the average temperature in PNP_DDSCR is lower than that in DDSCR and the ability of PNP_DDSCR to dissipate heat is more perfect. Comparing with DDSCR, the conclusions are obtained. Under the condition of transmission line pulse (TLP) test simulation analyses, the triggering voltage is reduced by 31%, the holding voltage is increased by 16.8%, the ESD design window is optimized by 44.5%, and on-resistance is lower. When TLP stress is 2.67 A, the average temperature of PNP_DDSCR is much lower than that of traditional DDSCR in the whole conduction process. With the increase of pulse lasting time, average temperature difference between two devices becomes great further. According to the very fast TLP (VF-TLP) testing results, clamping capability of PNP_DDSCR under transient overshoot voltage is more stable under the condition of fast turn-on speed. When the VF-TLP stress is 0.1 A, the overshoot voltage of PNP_DDSCR device is the 37% of that of DDSCR device while the PNP_DDSCR maintains a relatively fast triggering speed. Thus, the ESD protection capability of PNP_DDSCR is superior.

Area-efficient dual-diode with optimized parasitic bipolar structure for rail-based ESD protections

Lateral parasitic PNP transistor inside P+/N-well diode is explored and investigated for the electrostatic discharge (ESD) protections in I/O interface integrated circuits (ICs). An analysis for the breakdown behavior of the lateral parasitic PNP transistor with base floating is presented for the first time. Simulations on the lateral parasitic PNP transistor have been performed to understand the effects of geometry parameters on current gain β, triggering voltage Vt1 and on-resistance RON. The test structures were fabricated using the UMC 65 nm low-k logic/mixed-mode CMOS process and characterized with the transmission line pulse (TLP) system. The TLP characterization results demonstrate that the triggering voltage Vt1 is strongly influenced by the base region (i.e., base width), and on-resistance RON is mainly affected by the collector region (i.e., collector width) for the finger-type parasitic PNP. Meanwhile, the scalability of thermal failure current It2 has been studied in terms of the periphery of the lateral parasitic PNP and the whole device width.

Low-Noise Chopper Amplifier Using Lateral PNP Input Stage With Automatic Base Current Cancellation

This brief presents a low-noise chopper amplifier that uses a lateral PNP input stage with automatic base current cancellation in complementary metal–oxide–semiconductor (CMOS) process. A bipolar junction transistor (BJT) input stage can achieve lower noise level than the MOS transistor input stage, but its base current causes low DC input impedance. To enhance the DC input impedance of the BJT input stage, an automatic base current cancellation circuit is implemented using a 10-bit current digital-to-analog converter (DAC) and a successive approximation register (SAR) logic. The output current of the DAC tracks the base current of the BJT input stage using a binary search operation of the SAR logic, and the current DAC provides a cancellation current to the base of the BJT input stage to cancel the input base current. The amplifier is implemented in 0.18- $\mu \text{m}$ CMOS process, and the proposed amplifier occupies an active area of 0.297 mm2. The current consumption of the chopper amplifier is 146 $\mu \text{A}$ with 3.3 V supply voltage. The input referred noise of the chopper amplifier is 5.53 nV $/\surd $ Hz. The input bias current of the proposed amplifier with lateral PNP input stage implementing automatic base current cancellation is 0.391 nA.

Quantitative comprehension the impact of X-light on current gain of lateral PNP bipolar transistor

Bias emission voltage and dose-dependent current gain are the key parameters to detect the physical performance of bipolar transistors. Firstly, the effect of X-light with energy 22.1 and 25.0 keV from 109Cd on the current gain of lateral PNP bipolar transistors is measured. The substantial difference of current gain with the variation of bias and emission voltage is observed. Then, on basis of the outcomes of the nonlinear curve fitting approach, the relationship between bias voltage and emission-related current gain is successfully explained by using the model of combination Maxwell Boltzmann statistical with Bose-Einstein probability. The simulation results are in good agreement with the observed curves (current gain vs. voltage). The minimal correlation coefficient between experimental data and computed data is 0.998. In all cases considered, the mean relative error between the measured value and the model value is not more than 5.0%. Finally, the mathematical link between the parameters of current gain and voltage and the X-light dose is obtained. Therefore, using only one function, the current gain can be anticipated by the voltage and dose between bias and emission. The influence of X-light on the current gain of transverse PNP bipolar transistors is firstly discussed quantitatively.

Radiation mechanism of gate-controlled lateral PNP bipolar transistors in the hydrogen environment

Hydrogen plays a crucial role in realizing modern silicon devices. Molecular hydrogen may be found in processes of integrated circuit fabrication and packaging, such as wafer cleaning procedure, film depositions, high- and low-temperature anneal and die attachment by forming gas. It has been shown that hydrogen has strong effects on the total dose and dose rate response to bipolar devices. In order to study the relationship between hydrogen and radiation-induced products, we preform two experiments by using gate-lateral PNP transistors. In the first experiment, one set of devices is soaked in 100% hydrogen gas for 60 h and another set is not soaked, they are together irradiated at 5 rad(Si)/s to a total dose of 50 krad(Si). In the second experiment, devices are irradiated at 50 rad(Si)/s to 100 krad(Si), and then one group is annealed in 100% hydrogen gas and the other is annealed in the air for 40 h at the same temperature. The results show that the damage to devices which are soaked in hydrogen before irradiation is stronger than the devices that are not soaked, the anneal characteristics of devices in hydrogen gas are also changed more greatly than in the air. So the hydrogen can enhance the radiation and anneal damage to bipolar transistors. Using the gate-sweep technique, the radiation-induced products are separated and show that the hydrogen that enters into the transistor will cause the interface traps to increase and oxide trapped charge to decrease. The main reason is that the hydrogen can react with the oxide trapped charge to produce protons which can transport to the Si/SiO&lt;sub&gt;2&lt;/sub&gt; interface, and then react with H-passivized bond to create interface trap. Based on the reaction mechanism presented in our work, a numerical model of enhanced low dose rate sensitivity including molecular hydrogen reaction and proton generation mechanism is established. The simulation results for the density of interface traps and oxide trapped charge show a trend consistent with the experimental data, which verifies the correctness of the damage mechanism. This research provides not only the basis of the study of damage mechanism of bipolar devices, but also the powerful support for hydrogen soaking irradiation acceleration method.

Quantitative study of the effect of gamma radiation on lateral PNP bipolar transistor

Bias-emission voltage and dose-dependent current gain is a key parameter in detecting the physical properties of the bipolar transistor. The first objective of this work is to measure the influences of gamma radiation on current gain in lateral PNP bipolar transistors. Substantial differences of the current gain as a function of voltage between bias and emission are observed. Then, based on the calculated results from the non-linear curve fitting method, the voltage between bias and emission-dependent current gain is theoretically explained successfully via the asymmetric peak function. The simulations agree very well with the observed curves (current gain versus voltage). The minimum correlation coefficient between the experimental and calculated data is 0.998. The average relative errors between the measured and modeled values do not exceed 9.14% in all considered cases. Finally, the mathematical relationships between the parameters, which serve to link the current gain and voltage together with dose, are obtained. Consequently, the current gain can be predicted by both voltage between bias and emission and dose using only one function. To the best knowledge of the author, the effects of gamma irradiation on the lateral PNP transistors are quantitatively discussed for the first time in current gain.

A 5.43 nV/√Hz Chopper Operational Amplifier Using Lateral PNP Input Stage with BJT Current Mirror Base Current Cancellation

This paper presents a low-noise chopper operational amplifier using a lateral PNP input stage with bipolar junction transistor (BJT) current mirror base current cancellation. The BJT has a lower noise characteristic than the metal–oxide–semiconductor (MOS) transistor, where low-noise characteristics can be achieved by implanting the BJT to the input stage of the amplifier; however, the base current of the BJT input stage causes low input impedance of the amplifier. The BJT current mirror base current cancellation technique is implemented to enhance the input impedance of the BJT input stage by canceling the base current. BJT current mirror base current cancellation is implemented with a simple scheme using NPN transistors with deep n-well in a generic complementary metal–oxide–semiconductor (CMOS) process. For further noise reduction with the BJT input stage, a chopper amplifier scheme is adopted to reduce low-frequency components such as 1/f noise terms in the low-frequency range. The prototype chip is fabricated in a 0.18-μm CMOS process. The active area of the prototype amplifier is 0.213 mm2. The measured input-referred noise is 5.43 nV/√Hz. The measured input base current of the amplifier with base current cancellation is 67.971 nA. The total amplifier current consumption is 278.3 μA, with a power supply of 3.3 V.

Analytical model for total ionizing dose-induced excess base current in PNP BJTs

This work analytically models the crucial physical mechanisms accountable for the defect kinetics and the degradation of base current in PNP BJTs. Both the space charge and bimolecular mechanisms have been incorporated to elicit the defect dynamics (oxide charge and interface trap) following ionization radiation. Thereafter, two novel insights into the ionization damage on SiO2 of bipolar structure are provided, which includes the coupled effect of the two defect mechanisms and the existence of an “additional” hydrogen sensitivity in the bimolecular mechanism. A previous device model has been updated to describe the response of base current degradation to defects build-up. Further, a closed-form compact expression for the excess base current is provided, which is an explicit function of the total ionizing dose, dose rate, and hydrogen concentration. The new model closely fits the experimental data from several devices, including RF25 capacitor, gate controlled lateral PNP BJT, and LM124 amplifier. Our model delivers a practical approach to deduct the oxide charge modulation effect on excess base current. Thereafter, the relation between the modified excess base current and total ionizing dose is linear. Furthermore, this work suggests a practical approach, called as “offset current approach”, to predict the excess base in PNP BJTs at low dose rate.

A high-order curvature compensated voltage reference based on lateral BJT

This paper presents a curvature compensated voltage reference (VR), which is based on lateral PNP bipolar junction transistor (BJT). The proposed VR is fabricated in 0.18 μm CMOS process. The circuit consists of two first-order current-mode band gap references (BGR) and a subtraction circuit. Temperature characteristics of lateral PNP BJT is utilized for temperature curvature compensation. Moreover, in order to reduce the errors introduced by the conventional subtraction circuit, an improved subtraction circuit is proposed for improving performance of curvature compensation. Test results of prototype chips show the proposed VR has an average 2.36 ppm/° C within temperature range of −40 ° C to 120 °C. Power supply rejection ratio (PSRR) of the proposed VR achieves 69.5 dB at 100 Hz.

Effects of pre-irradiated thermal treatment on ideal factor of excess base current in bipolar transistors

&lt;sec&gt;During the service of the spacecraft, it will be disturbed by the energetic particles and rays, and thus induce total ionizing dose (TID), displacement damage (DD) or single event effect (SEE) to generate inside the electronic system, which can seriously affect the service lifetime of the electronic components. The difference in structure and types of electronic components are less sensitive to the radiation effects, but bipolar transistor is strongly sensitive to ionizing radiation effect. As a basic component of bipolar circuits, the in-depth study of bipolar transistor ionization radiation effect is of significance for engineering.&lt;/sec&gt;&lt;sec&gt;It has been shown that the an amount of hydrogen can inevitably introduced from an external source during the sealing process of the devices. The KOVAR alloy is widely used as a metal cap material of bipolar transistor in the process of encapsulation. The residual gas analysis (RGA) for sealed Kovar lid packages is shown to have 1%–2% of the hydrogen in the cavity. The source of the hydrogen is generally considered to be out-gassing from the gold plating on the KOVAR. So far, the researches have focused on the study of the ionization damage effect of bipolar transistors with different structures under &lt;sup&gt;60&lt;/sup&gt;Co gamma ray irradiation. There is lack of systemic study on the comparison of transistors packaged with and without cap.In this paper, we study the influence of sealed KOVAR lid packaged on ionizing radiation damage of lateral PNP bipolar transistor (LPNP) by using &lt;sup&gt;60&lt;/sup&gt;Co gamma ray as an irradiation source. The semiconductor parameter analyzer is used to measure the electrical parameters of LPNP transistor during irradiation. The irradiation defects in LPNP transistors packaged with and without cap are characterized by deep level transient spectroscopy (DLTS). Experimental results show that the LPNP transistors packaged with and without cap have similar electrical characteristics. The base current increases with the total dose increasing, while the collector current remains almost constant. The degradation of LPNP transistor packaged with cap is more serious.&lt;/sec&gt;&lt;sec&gt;According to the excess base current varying with base-emitter voltage for the LPNP transistors packaged with and without cap, the degradation of bipolar transistor packaged with cap is more serious under the same irradiation conditions. According to the analysis of DLTS, comparing with bipolar transistor packaged without cap, the signal peak at about 300 K is shifted to the left for the bipolar transistor packaged with cap. These results indicate that the LPNP transistors packaged with cap can generate more interface states during irradiation, which is attributed to a large amount of hydrogen and water vapor out-gassing from the gold plating on the KOVAR, which is released under the thermal stress. In the sealed environment, hydrogen can only diffuse into the device cavity, and is combined with the metal material in the transistor to form metal hydride. Therefore the degradation of transistor is severe under the same irradiation condition.&lt;/sec&gt;

An LTspice Simulation Model of Gamma-radiation Effects and Annealing in a Voltage Regulator With a Lateral Serial PNP Transistor With Round Emitters

The aim of this paper was to determine the reasons for a complex radiation response of the commercial-off-the-shelf LM2940CT5 low-dropout voltage regulator. Examination of this circuit in a gamma-radiation environment disqualified its use when operated with relatively high output currents, while its radiation tolerance was satisfactory when load current was approximately one-tenth (or lower) of the nominal value. In order to obtain a more thorough insight into the radiation response of this integrated circuit, a detailed SPICE model was developed. This model enabled mutual comparison of the influence of serial and driver PNP power transistor parameters: forward emitter current gain, knee current and emitter resistance. The serial lateral PNP power transistor with round emitters was identified as the weakest element that crucially affected the entire circuit radiation tolerance. The effects of gamma-radiation were examined for total doses up to 500 Gy followed by three sequences of isothermal annealing. Detailed characteristics of Beta(Ic) were procured for four different kinds of bias and load conditions during irradiation. The emitter resistance increase of the serial power transistor was a primary reason for the low radiation tolerance of the entire voltage regulator; it was much more influential than the perceived decline of the PNP power transistor forward emitter current gain. The influence of bias and load conditions were analysed with buildup of interface traps and the oxide-trapped charge, which affected the radiation and post-irradiation response of the serial power transistor.

Effect of H2 on interface traps in the LPNP transistors caused by 3 MeV proton irradiations

In this paper, the effects of 3 MeV proton irradiations on gate controlled lateral PNP (GLPNP) transistors are investigated with and without molecular hydrogen (H2) soaking. The electrical parameters are measured in-situ during irradiation. Radiation defects indicated by 3 MeV protons are measured by deep level transient spectroscopy (DLTS). At a given the irradiation fluence, the degradation for the H2-soaked transistors is much larger than that for the non-soaked transistors. Excess base current (ΔIB) for the H2-soaked transistors is bigger than that for the non-soaked transistors at a given emitter-base voltage and the same irradiation fluence. According to the gate sweep (GS) curve, it can be calculated that the number of the interface traps of the H2-soaked transistors is significantly larger than that for the non-soaked transistors under the same fluence, as demonstrated by DLTS analyses. 3 MeV protons could mainly produce the ionization damage in the GLPNP transistors, displacement damage can be almost negligible. The results for the 70 keV electron irradiations further confirm that 3 MeV protons could mainly produce ionization damage in the GLPNP transistors and hydrogen can aggravate the formation of interface traps in GLPNP transistors.

Effect of protons located at different region in SiO2 layer on GLPNP transistors degradation

Based on 100-keV, 130-keV and 170-keV proton irradiations, the contribution of ionization damage to the electrical property degradation of gate controlled lateral PNP (GLPNP) transistors is investigated. The key electrical parameters are measured in-situ during irradiations. The radiation-induced defects are characterized by deep level transient spectroscopy (DLTS). Experimental results show that the same ionization dose of various energy protons caused different degradation of current gain in GLPNP transistors. The current gain of the irradiated transistors by 170-keV protons degrades obviously, while that of the irradiated transistors by 100-keV protons does not almost change. As the ionization dose increases, the excess base currents of the irradiated transistors by 170-keV and 130-keV protons increase. The ideality factor of the irradiated transistor by 170-keV protons changes, while that of the transistor irradiated by 130-keV protons does not change. The gate sweep (GS) curves show that the main ionization defects induced by different protons are the interface traps. Compared with the irradiated transistors by 100-keV and 130-keV protons, the irradiated transistors by 170-keV protons has a high gate sweep peak at the same dose indicating that the 170-keV protons induced more interface traps. Therefore, the protons located at different region in SiO2 of GLPNP transistors can induce different degree of degradation, and the location of the proton is closer to the Si/SiO2 interface, the number of the radiation-induced interface traps is the more.

Analysis of displacement damage effects on bipolar transistors irradiated by spallation neutrons

Displacement damage induced by neutron irradiation in China Spallation Neutron Source (CSNS) is studied on bipolar transistors with lateral PNP, substrate PNP, and vertical NPN configurations, respectively. Comparison of the effects on different type transistors is conducted based on displacement damage factor, and the differences are analyzed through minority carrier lifetime calculation and structure analysis. The influence of CSNS neutrons irradiation on the lateral PNP transistors is analyzed by the gate-controlled method, including the oxide charge accumulation, surface recombine velocity, and minority carrier lifetime. The results indicate that the total ionizing dose in CSNS neutron radiation environment is negligible in this study. The displacement damage factors based on 1-MeV equivalent neutron flux of different transistors are consistent between Xi’an pulse reactor (XAPR) and CSNS.

Hydrogen Soaking, Displacement Damage Effects, and Charge Yield in Gated Lateral Bipolar Junction Transistors

The effects of 70-keV and 1-MeV electron irradiations on gate-controlled lateral PNP (GLPNP) transistors are evaluated with and without molecular hydrogen (H2) soaking. At a given ionization dose, 1-MeV electron irradiation causes more degradation of current gain in GLPNP transistors that have not been soaked in H2 than 70-keV electrons. This is because linear bipolar transistors are sensitive to both ionization and displacement damage effects, and because 1-MeV electrons induce significant displacement damage in Si-based bipolar junction transistors and 70-keV electrons do not. In H2-soaked transistors, the degradation is much larger than in unsoaked devices, and similar amounts of degradation are observed for 70-keV electron irradiation and 1-MeV electron irradiation. This occurs because ionization–induced release, transport, and reactions of hydrogen in the bipolar-base oxide greatly enhance interface-trap buildup and dominate device response in H2-soaked devices, and because charge yield ratios for 70-keV and 1-MeV electron irradiations differ by less than ~20%.

Estimation of enhanced low dose rate sensitivity mechanisms using temperature switching irradiation on gate-controlled lateral PNP transistor**Project supported by the National Natural Science Foundation of China (Grant Nos. U1532261 and 1630141).

The mechanisms occurring when the switched temperature technique is applied, as an accelerated enhanced low dose rate sensitivity (ELDRS) test technique, are investigated in terms of a specially designed gate-controlled lateral PNP transistor (GLPNP) that used to extract the interface traps (Nit) and oxide trapped charges (Not). Electrical characteristics in GLPNP transistors induced by 60Co gamma irradiation are measured in situ as a function of total dose, showing that generation of Nit in the oxide is the primary cause of base current variations for the GLPNP. Based on the analysis of the variations of Nit and Not, with switching the temperature, the properties of accelerated protons release and suppressed protons loss play critical roles in determining the increased Nit formation leading to the base current degradation with dose accumulation. Simultaneously the hydrogen cracking mechanisms responsible for additional protons release are related to the neutralization of Not extending enhanced Nit buildup. In this study the switched temperature irradiation has been employed to conservatively estimate the ELDRS of GLPNP, which provides us with a new insight into the test technique for ELDRS.

The effect of ionization and displacement damage on minority carrier lifetime

Based on 1 MeV electrons and 40 MeV Si ion irradiations, the contribution of ionization and displacement damage to the decrease in the minority carrier lifetime of gate controlled lateral PNP (GLPNP) transistors is investigated by gate sweeping (GS) technique. Molecular hydrogen is employed to increase the ionization radiation sensitivity and help to understand the relationship between the minority carrier lifetime and ionization damage. Experimental results show that 1 MeV electrons mainly induce ionization damage to GLPNP transistors, 40 MeV Si ions primarily produce displacement defects in silicon bulk. For 40 MeV Si ions, with increasing the irradiation dose, the densities of interface trap and oxide charge are almost no change, the minority carrier lifetime obviously decreases. The decrease of the minority carrier lifetime is due to bulk traps induce by 40 MeV Si ions. For 1 MeV electrons, with increasing the irradiation dose, the densities of interface trap and oxide charge for the GLPNP with and without soaked in H2 increase, and the minority carrier lifetime decreases. Compared with the GLPNP transistors without soaking in H2, the density of the interface traps the irradiated GLPNP transistors by 1 MeV electrons and soaked in H2 are larger and the minority carrier lifetime is lower. Therefore, both ionization and displacement damage can induce the decreases in the minority carrier lifetime including bulk minority carrier lifetime and surface minority carrier lifetime.

Impact of nitride passivation layer on ionizing irradiation damage on LPNP bipolar transistors

Bipolar junction transistors (BJTs) are generally employed in spacecraft, due to their current drive capability, linearity and excellent matching characteristics. High-energy particles and cosmic rays in space environment remarkably affect electronic devices, especially in BJTs producing total ionizing dose, displacement damage or single event effect. Among them, ionizing irradiation effects on BJTs dominates. For BJTs, ionization damage can induce the oxide trapped charges in SiO2 layer and interface traps in Si/SiO2, resulting in more recombination base current and the degradation of current gain. Consequently, the accumulation of both oxide charges and interface traps causes an increase in the base current.#br#Passivation layer is also an important factor of the irradiation effects of BJTs. Previous works only studied the degradation of electrical properties of the devices with/without passivation layer induced by irradiation, and did not give an influence mechanisms of passivation layer on the irradiation respond of devices. Therefore, the irradiation damage mechanisms of the BJTs with or without nitride passivation layer are not clear so far.#br#In this paper, the impact of Si3N4 passivation layer on ionizing irradiation damage on lateral PNP bipolar transistors (LPNP) was studied by using 60Co gamma irradiation source. The KEITHLEY 4200-SCS semiconductor parameter analyzer was used to measure the relationship between the electrical properties of LPNP transistors and ionization dose, including the Gummel characteristics, the degradation of current gain, etc. The irradiation defects of the LPNP transistors with/without passivation layer structure were analyzed by the deep level transient spectroscopy (DLTS). The experimental results show that the electrical properties of the LPNP transistors with and without passivation layer exhibit similar characteristics. For all samples, the base current increases with increasing the total dose, while the collector current does not almost change. Compared with the LPNP transistors without Si3N4 passivation layer, the degradation of LPNP transistor with Si3N4 passivation layer is severe.#br#Based on the excess base current as a function of base-emitter voltage for the LPNP transistors with/without nitride passivation layer, the degradation of bipolar transistors with nitride passivation layer is severe under the same irradiation conditions. The DLTS analyses show that compared with the bipolar transistors without nitride passivation layer, the signal peak located at about 300 K is shifted to low temperature for the bipolar transistors with nitride passivation layer. The above results show that the LPNP transistors with nitride passivation could produce a large number of interface states with the energy level is closer to the middle of the forbidden band during the irradiation, which is attributed to a large number of hydrogen presence during the processing of fabricated passivation layer.