Area-efficient dual-diode with optimized parasitic bipolar structure for rail-based ESD protections

Abstract

Lateral parasitic PNP transistor inside P+/N-well diode is explored and investigated for the electrostatic discharge (ESD) protections in I/O interface integrated circuits (ICs). An analysis for the breakdown behavior of the lateral parasitic PNP transistor with base floating is presented for the first time. Simulations on the lateral parasitic PNP transistor have been performed to understand the effects of geometry parameters on current gain β, triggering voltage Vt1 and on-resistance RON. The test structures were fabricated using the UMC 65 nm low-k logic/mixed-mode CMOS process and characterized with the transmission line pulse (TLP) system. The TLP characterization results demonstrate that the triggering voltage Vt1 is strongly influenced by the base region (i.e., base width), and on-resistance RON is mainly affected by the collector region (i.e., collector width) for the finger-type parasitic PNP. Meanwhile, the scalability of thermal failure current It2 has been studied in terms of the periphery of the lateral parasitic PNP and the whole device width.