Lateral NPN Research Articles

ESD performance evaluation of field oxide lateral NPN transistors

The author analyses the ESD performance of two field oxide lateral NPN devices fabricated with classical or specific process steps over-doped p-well (ODPW). It is shown that ODPW devices lead to a higher ESD performance owing to a lower heat dissipation during stress.

Electrical properties of lateral npn junctions using molecular beam epitaxy grown Si-doped GaAs on patterned substrates

We investigated electrical properties of laterally aligned npn junctions formed with one-step molecular beam epitaxial growth of Si-doped GaAs on patterned substrates. Detailed current-voltage ( I- V) measurements of the lateral npn junctions showed asymmetric characteristics which suggest that the junction configuration is rather nn −pn with a highly compensated n − region than a simple npn configuration. Temperature dependence of the I- V curves was also examined. Cross-sectional electron beam induced current and transmitted electron microscope measurements revealed the critical angle of the crystal plane at which conduction type of Si-doping converts to be exactly 25°, i.e. (311)A plane.

Electrical properties of lateral npn junctions using molecular beam epitaxy grown Si-doped GaAs on patterned substrates

Electrical properties of lateral npn junctions using molecular beam epitaxy grown Si-doped GaAs on patterned substrates

Fabrication of in-plane-gate transistor structures by focused laser beam-induced Zn doping of modulation-doped GaAs/AlGaAs quantum wells

Local Zn doping of n-modulation-doped GaAs/AlGaAs quantum well samples induced by absorption of a focused laser beam has been used to fabricate in-plane-gate transistor structures. Laser-induced thermal Zn diffusion from a highly doped SiO2 emulsion into the sample surface layers allows direct writing of lateral npn structures with sub-μm resolution. The p-doped lines form lateral potential barriers which are efficiently isolating the gate electrodes for large applied voltages at room temperature. Transistor structures with a 3-μm-wide electron channel in between V-shaped gates yield a transconductance of about 50 μS and are pinched-off at gate voltages UG≤−2.0 V.

Analysis of ESD protection networks for DMOS power transistors by means of static and time‐resolved emission microscopy

AbstractDifferent ESD input/output protection networks, based on Zener diodes and lateral npn transistors have been implemented with the aim of characterizing their effectiveness in protecting vertical DMOS power transistors. Failure mechanisms have been identified by means of static emission microscopy. Gated emission microscopy, in synchronism with a voltage pulse emulating the ESD event, enables the dynamic behaviour of protection structures to be analysed, identifying lateral current crowding effects which explain the observed failure mechanisms.

Lateral npn junction and semi-insulating GaAs current confinement structure for index-guided InGaAs/AlGaAs lasers by molecular beam epitaxy

A current confinement structure with a lateral npn junction and a semi-insulating (SI) GaAs is examined for an index-guided InGaAs/AlGaAs strained quantum-well laser. Amphoteric doping of Si in GaAs and AlGaAs is used to form a lateral npn structure grown over a channeled patterned low-temperature-grown SI GaAs layer. A threshold current of 7.4 mA and total external differential quantum efficiency of 59% under room-temperature continuous-wave (CW) operation are achieved with devices fabricated by a self-aligned process. A device with antireflection-high-reflection (AR-HR) coating had a light output over 300 mW.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Protecting N-channel output transistors from ESD damage

The advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has led to the use of Lightly Doped Drain (LDD) and metal clad, or silicided gate/source/drain processes. There has been a marked decrease in the Electrostatic Discharge (ESD) withstand threshold of these advanced processed Integrated Circuits (ICs), specifically on the output (O) and input/ output (I/O) pins. Damage from 1000 to 2000 volt Human Body Model (HBM) ESD events tend to occur in the drain of the N-channel output pull-down transistor and not in the protection circuit. On the other hand, the protection circuit on input pins (i.e. IC pins which do not have output transistors connected to them) is damaged at ESD withstand threshold levels of ⩾ 3500 volts. On the O and I/O pins, the parasitic lateral NPN bipolar structures of the outpul pull-down transistor and the protection circuit compete to discharge the ESD current. This study shows: (1) that the base widths of these parallel structures are critical factors in determining the current discharge path during the ESD event; and (2) that the ESD withstand threshold can be increased by ⩾ 2000 V if the failure site is switched from the output transistor drain to the protection circuit.

Low threshold InGaAs strained quantum well laser with lateral npn current blocking structure grown by molecular beam epitaxy

A sophisticated current confinement structure using the amphoteric nature of MBE grown Si-doped GaAs and AlGaAs is demonstrated for an index-guided InGaAs strained quantum well laser. Lateral and vertical npn current blocking layers were formed for the first time by a selfaligned process. Devices showed threshold current of 10 mA and total slope efficiency of 0.56 under room temperature CW operation.

Modelling of the sidegating and the backgating effects in GaAs MESFETs

Sidegating and backgating effects affect the I/V characteristics of a GaAs MESFET built on SI substrates. The basic charge trapping process can be related to current flowing through the channel-substrate interface. This effectively changes the channel thickness. For the side-gating effect, the observed voltage threshold for current pinch-off is explained by the breakdown of a parasitic lateral npn transistor. An equivalent circuit model is put forward to include the sidegating and backgating effects. Reasonable results have been obtained during simulation.

(MI)/SUP 2/L: multiinput-multioutput integrated injection logic

The (MI) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> L structure will be discussed, which is a combination of CHL/CHIL and I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> L, taking advantage of ion implantation. It provides improved speed-power product and functional density compared to conventional I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> L schemes. The gate consists of a lateral npn transistor with intermediate collectors and a Schottky-inverter. The device fabrication is fully compatible with standard bipolar processes for analog circuits. The approach is applied to standard bipolar process of 6 μm epi-thickness and 35 V breakdown voltage. The results obtained are a minimum power-delay product of .07 pJ and a minimum delay of 15 ns at .38 pJ. The improved device parameters, packing density and design flexibility are discussed with the experimental results of test circuits, including a D-type frequency divider and MS flip-flop.