Protecting N-channel output transistors from ESD damage

Abstract

The advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has led to the use of Lightly Doped Drain (LDD) and metal clad, or silicided gate/source/drain processes. There has been a marked decrease in the Electrostatic Discharge (ESD) withstand threshold of these advanced processed Integrated Circuits (ICs), specifically on the output (O) and input/ output (I/O) pins. Damage from 1000 to 2000 volt Human Body Model (HBM) ESD events tend to occur in the drain of the N-channel output pull-down transistor and not in the protection circuit. On the other hand, the protection circuit on input pins (i.e. IC pins which do not have output transistors connected to them) is damaged at ESD withstand threshold levels of ⩾ 3500 volts. On the O and I/O pins, the parasitic lateral NPN bipolar structures of the outpul pull-down transistor and the protection circuit compete to discharge the ESD current. This study shows: (1) that the base widths of these parallel structures are critical factors in determining the current discharge path during the ESD event; and (2) that the ESD withstand threshold can be increased by ⩾ 2000 V if the failure site is switched from the output transistor drain to the protection circuit.